Semiconductor memory device for achieving high bandwidth and met

Details Semiconductor memory device for achieving high bandwidth and met Semiconductor memory device for achieving high bandwidth and met

1995-05-22

1997-04-15

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365 51, 36523003, G11C 506

Patent

active

056216793

ABSTRACT:
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device and a method for arranging a signal line therein which can realize a high bandwidth by embodying a chip architecture being comprised of a multi I/O line. A semiconductor memory device includes arrays comprised of a plurality of reference blocks for storing a plurality of memory cells, a plurality of word lines extending in the direction of length of a chip, a plurality of bit lines extending in a vertical direction of length of a chip, each pair of bit lines being comprised of a bit line and a complementary bit line, a plurality of data I/O lines arranged on the upper portion of the arrays and extending in the vertical direction, each pair of data I/O lines being comprised of a data I/O line and a complementary data I/O line and being one by one connected to each pair of bit lines, and a plurality of column selection lines arranged in the vertical direction and adjacent to the data I/O line and complementary data I/O line, for controlling connection of each pair of bit lines to the data I/O lines.

REFERENCES:
patent: 5291432 (1994-03-01), Furutani
patent: 5293559 (1994-03-01), Kim et al.
patent: 5325336 (1994-06-01), Tomishima et al.
patent: 5457648 (1995-10-01), Eisig

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