Semiconductor memory device fixing defective memory cell selecti

Details Semiconductor memory device fixing defective memory cell selecti Semiconductor memory device fixing defective memory cell selecti

1997-08-27

1998-10-20

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365205, 365207, 365226, G11C 700

Patent

active

058256997

ABSTRACT:
In a DRAM, an N-channel MOS transistor is connected between a forward end portion of each column selection-line and a signal transmission line for transmitting a sense amplifier driving signal. The N-channel MOS transistor is brought into a conducting state in a period when the signal goes low for activation and a column decoder is inactivated. Thus, a disconnected defective column selection line can be prevented from being charged at a high level and causing a malfunction of the DRAM. Further, no specific line of a ground potential GND may be provided for the N-channel MOS transistor dissimilarly to the prior art, whereby the layout area can be reduced.

REFERENCES:
patent: 4074237 (1978-02-01), Spampinato
patent: 5255228 (1993-10-01), Hatta et al.
patent: 5274594 (1993-12-01), Yanagisawa et al.
patent: 5363331 (1994-11-01), Matsui et al.
patent: 5579266 (1996-11-01), Tahara
patent: 5666315 (1997-09-01), Tsukude et al.

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