Semiconductor memory device facilitated with plural self-refresh

Static information storage and retrieval – Read/write circuit – Data refresh

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365233, 365236, G11C 700

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active

054673151

ABSTRACT:
The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal. Such availability of plural self-refresh modes becomes particularly advantageous when considering consumption of the back-up power for maintaining the IC memory device versus stability of stored data. While the consumption of the back-up power for maintaining the device would be relatively lower under one of the self-refresh modes, namely, the PS (pseudo) refresh mode, the stability of data stored would, however, be greater under another self-refresh mode, namely, the VS (virtual) refresh mode.

REFERENCES:
patent: 4716551 (1987-12-01), Inagaki
patent: 4811295 (1989-03-01), Shinoda
patent: 4972376 (1990-11-01), Torimaru et al.
patent: 5146430 (1992-09-01), Torimaru et al.
Hitachi IC Memory Data Book, Hitachi, Ltd., Mar. 1987, pp. 229-234.

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