Semiconductor memory device executing a memory test in a plurali

Details Semiconductor memory device executing a memory test in a plurali Semiconductor memory device executing a memory test in a plurali

1994-09-20

1996-09-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518903, 36523006, G11C 700

Patent

active

055530257

ABSTRACT:
A semiconductor memory device comprises an address bus having plural bits for designating addresses included in a first address group assigned to a memory cell array and in a second address group assigned to plural test modes, a first address decoder for decoding addresses in the first address group, and a second address decoder for decoding addresses in the second address group. A test commanding section generates a test commanding signal responsive to any one of addresses assigned to plural test modes. The second decoder acting as a test mode selecting section is activated by the test commanding signal to generate a test mode selecting signal from addresses assigned to the test modes. A test performing section tests inside the memory device in one of the test modes based on the test mode selecting signal. Number of data items to be input for executing a test inside the memory device is reduced without increasing an external pins.

REFERENCES:
patent: 4603405 (1986-07-01), Michael
patent: 5134587 (1992-07-01), Steele
patent: 5177745 (1993-01-01), Rozman
patent: 5315554 (1994-05-01), Nanba

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