Semiconductor memory device equipped with serial/parallel...

Details Semiconductor memory device equipped with serial/parallel... Semiconductor memory device equipped with serial/parallel...

2000-03-20

2001-11-13

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S220000, C365S221000, C365S189080, C365S193000, C365S233100, C714S722000, C714S718000

Reexamination Certificate

active

06317372

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which inputs/outputs data from/to the exterior in the form of serial data, and which reads/writes data from/into memory cells in the form of parallel data.
In addition, the present invention relates to a semiconductor integrated circuit which has testing modes for the data read/write tests of memory cells. More particularly, it relates to techniques for reducing testing costs.
2. Description of the Related Art
A DDR-SDRAM (Double Data Rate Synchronous DRAM)or the like have been known as semiconductor integrated circuits in each of which data are inputted/outputted from/to the exterior in series, and data are read/written from/into memory cells in parallel. The DDR-SDRAM inputs/outputs data from/to the exterior in synchronization with both the rising edge and the falling edge of a data strobe signal DQS, and thus permits the write/read of the data to proceed at high speed.
FIG. 1
shows the outline of the DDR-SDRAM of this kind.
The DDR-SDRAM
1
comprises an input data latching unit
2
, an output data latching unit
3
, an address inputting unit
4
, a predecoder
5
, a timing controlling unit
6
, a command decoder
7
, a memory core unit
8
, input buffers
9
, and pads
10
. Actually, a plurality of memory core units
8
are formed in a chip.
The input data latching unit
2
accepts a data signal DQ and a data strobe signal DQS (as signals DQIN and DQSIN) through the input buffers
9
, and outputs write data signals GWED, GWOD. This input data latching unit
2
receives a data address signal GCA and an internal clock signal LCLK
0
.
The output data latching unit
3
receives the data address signal GCA and internal clock signals CLK
0
, CLK
180
, and it accepts read data signals GRED, GROD from the memory core unit
8
, and outputs the accepted data as the data signal DQ.
The address inputting unit
4
accepts an address signal AD from the exterior in synchronization with a clock signal CLK and outputs the accepted data as an internal address signal ADIN.
The predecoder
5
receives the internal address signal ADIN and a timing signal Ti, and outputs a predecoded signal PDEC.
The timing controlling unit
6
receives the clock signal CLK, a clock signal/CLK and a control command signal CMD
1
, and outputs the internal clock signals CLK
0
, CLK
180
, LCLK
0
, the data address signal GCA, an enable signal EN and the timing signal T
1
.
The command decoder
7
receives the clock signal CLK and a command signal CMD, and outputs the control command signal CMD
1
and test command signals TEST
1
, TEST
2
. The test command signal TEST
1
is a signal which becomes a high level during a DDR data compression test mode and an SDR data compression test mode to be explained later. On the other hand, the test command signal TEST
2
is a signal which becomes a high level during the SDR data compression test mode.
The memory core unit
8
is constructed of an even-numbered core unit
8
a
and an odd-numbered core unit
8
b
. Each of the even-numbered core unit
8
a
and the odd-numbered core unit
8
b
includes a write controlling circuit
11
, a write amplifier
12
, a read amplifier
13
, a sense amplifier
14
, a decoder
15
, and a memory cell area
16
having a plurality of memory cells (memory cell areas
16
a
,
16
b
corresponding to the respective core units
8
a
, B
b
). The even-numbered core unit
8
a
is a circuit which is activated when an address signal A
0
(the lowest address) is brought to a low level. In contrast, the odd-numbered core unit
8
b
is a circuit which is activated when the address signal A
0
is brought to a high level.
The write controlling circuit
11
is a circuit which transmits the write data signal GWED or GWOD to the write amplifier
12
. Further, the write amplifier
12
is a circuit which outputs the write data signal GWED or GWOD to the sense amplifier
14
. Besides, the read amplifier
13
is a circuit which outputs data amplified by the sense amplifier
14
, as the read data signal GRED or GROD. In addition, the decoder
15
is a circuit which receives the predecoded signal PDEC and which outputs a decoded signal (not shown). The write data signals GWED, GWOD and the read data signals GRED, GROD are signals which are used in common by all the memory core units
8
, and the lengths of wiring for the signals are long.
Incidentally, an expression “/” as in the clock signal /CLK signifies the negative logic. Each signal indicated by a bold line consists of a plurality of signals. By way of example, the read data signal GRED (or GROD) is composed of read data signals GRED
0
, GRED
1
, GRED
2
and GRED
3
(or read data signals GROD
0
, GROD
1
, GROD
2
and GROD
3
). Likewise, the write data signal GWED (or GWOD) is composed of write data signals GWED
0
, GWED
1
, GWED
2
and GWED
3
(or write data signals GWOD
0
, GWOD
1
, GWOD
2
and GWOD
3
). The read data signals GRED
0
-GRED
3
, GROD
0
-GROD
3
and the write data signals GWED
0
-GWED
3
, GWOD
0
-GWOD
3
correspond to data signals DQ
0
-DQ
3
, respectively.
FIG. 2
shows the input data latching unit
2
for a data signal DQ
0
. Each of input data latching units for data signals DQ
1
-DQ
3
is the same as the input data latching unit
2
.
The input data latching unit
2
includes flip-flop circuits
17
a
,
17
b
,
17
c
, transmitting circuits
18
,
19
, and a data switching circuit
20
.
The flip-flop circuit
17
a
accepts an internal data signal DQIN
0
in synchronization with the rise of the internal data strobe signal DQSIN, and outputs a write data signal DU
0
. Subsequently, the flip-flop circuit
17
b
accepts the write data signal DU
0
in synchronization with the fall of the internal data strobe signal DQSIN, and outputs a write data signal DU. Further, the flip-flop circuit
17
c
accepts the internal data signal DQIN
0
in synchronization with the fall of the internal data strobe signal DQSIN, and outputs a write data signal DL.
The transmitting circuit
18
includes CMOS (complementary metal-oxide-semiconductor) transmission gates
18
a
,
18
b
in each of which the sources and drains of a pMOS (p-channel MOS) transistor and an nMOS (n-channel MOS) transistor are connected to each other, and an inverter
18
c
. Hereinbelow, the pMOs transistor and nMOS transistor shall be simply termed the “pMOS” and “nMOS”, respectively. The CMOS transmission gate
18
a
receives the write data signal DU and outputs a write data signal DU
2
. On the other hand, the CMOS transmission gate
18
b
receives the write data signal DL and outputs a write data signal DL
2
. The gates of the pMOS 's (pMOS transistors) of the CMOS transmission gates
18
a
,
18
b
receive the inverted signal of an internal data strobe signal DS through the inverter
18
c
. Also, the gates of the nMOS's (nMOS transistors) of the CMOS transmission gates
18
a
,
18
b
receive the internal data strobe signal DS. Here, the internal data strobe signal DS is a signal which reatains a high level for a predetermined time period when the data strobe signal DQS is at a low level.
The switching circuit
20
includes CMOS transmission gates
20
a
,
20
b
,
20
c
,
20
d
in each of which the sources and drains of a pMOS and an nMOS are connected to each other, and an inverter
20
e
. The CMOS transmission gates
20
a
,
20
c
receive the write data signal DU
2
and outputs the received signal as write data signals WED
0
, WOD
0
, respectively. On the other hand, the CMOS transmission gates
20
b
,
20
d
receive the write data signal DL
2
and outputs the received signal as the write data signals WED
0
, WOD
0
, respectively. The gates of the pMOS's of the CMOS transmission gates
20
a
,
20
d
and those of the nMOS's of the CMOS transmission gates
20
b
,
20
c
receive the inverted signal of the data address signal GCA through the inverter
20
e
. Also, the gates of the nMOS's of the CMOS transmission gates
20
a
,
20
d
and those of the pMOS's of the CMOS transmission gates
20
b
,
20

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