Semiconductor memory device equipped with refresh timing...

Details Semiconductor memory device equipped with refresh timing... Semiconductor memory device equipped with refresh timing...

2002-10-10

2004-02-17

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030

Reexamination Certificate

active

06693838

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a pseudo static random access memory (Pseudo SRAM) or the like, and in particular, to a semiconductor memory device having a function capable of selecting a block to hold data in a memory array divided into a plurality of blocks.
2. Description of the Prior Art
FIG. 6
is a circuit diagram showing a construction of a refresh timing signal generator circuit
152
-
5
of a prior art example. The refresh timing signal generator circuit
152
-
5
of
FIG. 6
is provided for hidden refresh executed by itself for a semiconductor memory device that is the so-called “Pseudo SRAM”, which is provided with DRAM type memory cells and has an input and output interface compatible with the asynchronous type SRAM.
The refresh timing signal generator circuit
152
-
5
of
FIG. 6
is provided with a reference voltage generator circuit
1
for generating a reference voltage VN and a ring oscillator
2
for generating a refresh timing signal &phgr; of a predetermined period in accordance with the reference voltage VN generated as described above.
In the reference voltage generator circuit
1
of
FIG. 6
, a supply line Vdd of a power voltage is connected to a drain of a P-channel field-effect transistor (hereinafter referred to as a P-channel FET) P
1
, and a source thereof is connected to the gate thereof and is connected to the source of a drain-grounded N-channel field-effect transistor (hereinafter referred to as an N-channel FET) N
1
, and the gate of a P-channel FET P
2
. Moreover, the supply line Vdd of the power voltage is connected to the drain of the P-channel FET P
2
via a resistor R
1
, and the source thereof is connected to a source and a gate of a drain-grounded N-channel FET N
2
and the gate of the N-channel FET N
1
. In the reference voltage generator circuit
1
constructed as above, at the connection point of the source of the P-channel FET P
2
and the source of the N-channel FET N
2
, a predetermined reference voltage VN based on the power voltage Vdd is generated so as to be supplied to a ring oscillator
2
.
In the ring oscillator
2
of
FIG. 6
, the reference voltage VN from the reference voltage generator circuit
1
is inputted to the gates of five N-channel FETs N
4
, N
6
, N
8
, N
10
and N
12
. A CMOS type inverter IN
1
constructed of a P-channel FET P
3
and an N-channel FET N
3
, and an N-channel FET N
4
that is connected to the grounded side of the N-channel FET N
3
and is controlled by the reference voltage VN constitute an inverter AP
1
provided with an amplification function. Likewise, a CMOS type inverter IN
2
constructed of a P-channel FET P
4
and an N-channel FET N
5
, and an N-channel FET N
6
that is connected to the grounded side of the N-channel FET N
5
and is controlled by the reference voltage VN constitute an inverter AP
2
provided with an amplification function. Further, a CMOS type inverter IN
3
constructed of a P-channel FET P
5
and an N-channel FET N
7
, and an N-channel FET N
8
that is connected to the grounded side of the N-channel FET N
7
and is controlled by the reference voltage VN constitute an inverter AP
3
provided with an amplification function. Yet further, a CMOS type inverter IN
3
constructed of a P-channel FET P
6
and an N-channel FET N
9
, and an N-channel FET N
10
that is connected to the grounded side of the N-channel FET N
9
and is controlled by the reference voltage VN constitute an inverter AP
4
provided with an amplification function. Yet further, a CMOS type inverter IN
5
constructed of a P-channel FET P
7
and an N-channel FET N
11
, and an N-channel FET N
12
that is connected to the grounded side of the N-channel FET N
11
and is controlled by the reference voltage VN constitute an inverter AP
5
provided with an amplification function. These five-stage inverters AP
1
to AP
5
each provided with the amplification function are connected in series, and an output signal from the inverter AP
5
provided with the amplification function is negatively fed back to the input of the first-stage inverter AP
1
provided with the amplification function, constituting an oscillator circuit. In the ring oscillator
2
constructed as above, a refresh timing signal &phgr; having a predetermined period is generated in accordance with the inputted reference voltage VN and outputted.
In the refresh timing signal generator circuit
152
-
5
constructed as above, the refresh period, i.e., the oscillation frequency of the ring oscillator
2
is determined by the voltage level of the reference voltage VN and the number of stages (five stages in the construction of
FIG. 6
) of the inverters, which are each provided with the amplification function and constitute the ring oscillator. Therefore, the refresh period is constant regardless of the operation mode. Normally, the refresh period is set so as to become equal to or greater than a value obtained by dividing the refresh standard by the number of cycles for refreshing all the memory cells. For example, if the standard of the refresh period is 300 msec and the number of cycles is 8192, then the refresh period is set to 300 msec/8192=36 &mgr;sec.
In a semiconductor memory device that has a function capable of making an entry into a mode capable of selecting the block to hold data in the memory array divided into a plurality of blocks by means of an address key or the like (the function being hereinafter referred to as a data-hold block selection function), there has been a growing demand for suppressing the consumption of current when the number of blocks to hold data is small.
SUMMARY OF THE INVENTION
An essential object of the present invention is to solve the aforementioned problems and provide a semiconductor memory device capable of reducing the consumption of power in the case of a small number of selected blocks when the data-hold block selection function is used.
In order to achieve the aforementioned objective, according to one aspect of the present invention, there is provided a semiconductor memory device provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. In the semiconductor memory device, selecting means selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and signal generating means changes the refresh period according to a number of blocks selected by the selecting means and generating a refresh timing signal having a changed refresh period, and outputs a generated refresh signal.
In the above-mentioned semiconductor memory device, when the number of blocks selected by the selecting means is a natural number n, and the number of all the blocks of the memory cell array is a natural number m (m>n) equal to or larger than two, then the signal generating means preferably generates a refresh timing signal having a period of m
times the refresh period when the number of blocks selected by the selecting means is the number of all the blocks of the memory cell array, and outputs a generated refresh timing signal.
In the above-mentioned semiconductor memory device, an address of the block selected by the selecting means preferably has a specific address rule.
According to another aspect of the present invention, there is provided a semiconductor memory device provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. In the semiconductor memory device, setting means sets whether or not data is held at only a predetermined block in the memory cell array divided into a plurality of blocks, in accordance with a predetermined first command signal, and frequency dividing means divides a frequency of the refresh timing signal by a predetermined frequency division number in accordance with a

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