Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2005-05-17
2008-09-16
Chaudry, Mujtaba K. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S804000
Reexamination Certificate
active
07426683
ABSTRACT:
The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit200characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory120separate from main data stored in main memory110.In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit300corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.
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Handa Osamu
Kimizuka Hiroshi
Takahashi Hiroshi
Takegama Akihiro
Brady III Wade James
Chaudry Mujtaba K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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