Semiconductor memory device equipped with dummy cells

Details Semiconductor memory device equipped with dummy cells Semiconductor memory device equipped with dummy cells

2003-09-12

2004-06-15

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S208000, C365S051000, C365S072000, C365S222000

Reexamination Certificate

active

06751142

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device and more particularly to a semiconductor device including high reliable, high-speed and highly integrated memories using memory cells having an amplification ability.
As a dynamic random access memory (hereinafter referred to as “DRAM”), it is widely known to provide a configuration in which one transistor cell comprised of one-transistor and one-capacitor is applied as a memory cell. However, the semiconductor device in recent years shows some problems of a reduction in breakdown voltage characteristic of MOS transistor as a size of the MOS transistor is made fine and of an increased power consumption accompanied by a high density integration as the MOS transistor is processed to have a high density integration and scale down. As a result, its operative voltage becomes low to solve these problems and fulfill the requirement of further low power consumption. Due to this fact, no amplification ability is found in the memory cell itself in the DRAM having one-transistor cell. Consequently, an amount of read signals from the memory cell is low, and its operation may receive various kinds of noise and easily become unstable.
In view of this fact, as a memory cell capable of obtaining larger signal voltage through amplification ability, a memory cell, composed of three transistors, which has been employed before one-transistor cell is practically used (hereinafter referred to as “three-transistor cell”.) receives attention again.
The three-transistor cell has already been described in IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp.42-43, 1970, for example. As shown in
FIG. 2
, this memory cell (hereinafter called as “MCT”) is composed of NMOS transistors R, W, S. When a writing operation is carried out for the memory cell MCT, data is written into a memory node NS from a data bus DBUS through a transistor W. When stored information is read out, a transistor R is activated and a read bus RBUS is driven to a potential corresponding to a potential of the memory node NS.
Further, as another memory cell having an amplification ability, the capacitance-coupled type two-transistor cell composed of two transistors and one capacitor has already been described in IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp.132-133, 2000 (hereinafter referred to as a document No.1). As shown in
FIG. 3
, this memory cell MC is composed of a read NMOS transistor QR, a write transistor QW and a coupled-capacitance Cc. The read NMOS transistor QR is a normal MOSFET. In addition, each of the write transistor QW and the coupled-capacitance Cc is called in the document No.1 as a stacked tunnel transistor PLEDTR and a built-in capacitor, respectively.
A feature of this memory cell MC consists in, at first, a structure in which the read NMOS transistor QR and the write transistor QW are stacked up. Thus, a cell area can be made small. That is, an area of the memory cell having the prior art one-transistor employed therein is about 8 F
2
(F: Feature size (minimum machining size)) and to the contrary, an area of the memory cell MC using the two-transistor is as low as 4 to 6 F
2
.
A second feature of this memory cell MC consists in reduction of a leak current under application of the write transistor utilizing a tunneling effect. With such an arrangement as above, although a refreshing operation is also required in the same manner as that of the prior art DRAM, its frequency in operation is well decreased as compared with that of the prior art.
These elements are connected such that one end of the coupled-capacitance Cc and a gate terminal of the write transistor QW are connected to a word line WL and a source terminal of the write transistor QW is connected to a write data line DW (called as “data line” in the document No.1). The other end of the coupled-capacitance Cc and a drain terminal of the write transistor QW are connected to a gate terminal of the NMOS transistor QR, thus forming a memory node. Further, a source terminal of the read NMOS transistor QR is connected to the ground and the drain terminal is connected to the read data line DR (called as “a sense line” in the document No.1). When the stored information is read out, the read NMOS transistor QR is activated and the read data line DR is driven to a potential corresponding to a potential of the memory node.
To the contrary, a reading operation is carried out in the DRAM using the prior art one-transistor cell while a half value VDD/2 of the power supply voltage VDD is applied as a reference voltage. That is, one data line is driven to either VDD/2+VS or VDD/2′−VS in response to the stored information of the memory cell selected after the pair of data lines are precharged to VDD/2. Either a small potential +VS or a small potential −VS between one data line driven to this potential and the other data line held at the precharge potential is amplified by a sense amplifier and data is readout. That is, the stored information is discriminated in reference to either a positive or negative signal generated in the pair of data lines in response to the stored information in the memory cell.
However, when the memory cell showing the amplification ability described above is used, only signals having either one of the polarities are present as the signals generated in the pair of data lines. For example, when the stored information “1” of high potential where the transistor S is brought into conduction in the memory cell MCT shown in
FIG. 2
is held in the memory node NS, the word line WL is driven to the read potential. Consequently, the transistor R is brought into conduction and the one data-line precharged to VDD/2, for example, is discharged toward the ground potential. At this time, negative signals can be obtained at the pair of data lines. In turn, when a low potential stored information “0” in which the transistor S is turned off is held at the memory node NS, even if the word line WL is driven to the read potential and the transistor R is activated, the transistor S is not brought into conduction. Therefore, the data line is held at the precharge potential VDD/2. Thus, no potential is generated at the pair of data lines, so that the stored information cannot be discriminated. A similar problem may also occur in the memory cell MC shown in FIG.
3
.
In view of the foregoing, as a reading method to resolve the aforesaid problems in a memory cell having amplification ability, there has already been proposed a method disclosed in Japanese Patent Laid-open No. 9-213812, for example. In this prior art, a memory cell composed of a memory MIS (Metal Insulator Semiconductor) transistor M
1
and a read MIS transistor Q
1
isolated by an insulation film. Further, a dummy cell is connected to each of the read data lines. As this dummy cell in the aforesaid memory cell, the dummy cell in which the gate length of the memory MIS transistor M
1
is set to about twice and the stored information of “1” is written into it is used. The pair of data lines is driven under application of such a memory cell and the dummy cell to read out the stored information.
In addition, in the prior art normal DRAM, the dummy cell was arranged one by one for every word line, data of one selected memory cell was driven and read out.
However, application of the method disclosed in the aforesaid Japanese Patent Laid-open No. 9-213812 to the memory cell array composed of the memory cell MC shown in
FIG. 3
causes the data line wiring for use in writing the stored information “1” to the dummy cell in some cases of the arrangement of the dummy cell and further causes a memory cell array area to be increased. For example, when the data lines of the memory cell and the power supply line for the dummy cell are formed at the same layer, it is necessary to form each of the lines so as to cause the data lines to avoid the power supply line in some cases of the arrangement of the memory cell and the dummy cell. Consequently

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