Semiconductor memory device employing multi-port RAMs

Details Semiconductor memory device employing multi-port RAMs Semiconductor memory device employing multi-port RAMs

1992-06-23

1994-06-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518903, 36518901, 36523005, G11C 700, G11C 1134, G06F 1516

Patent

active

053195965

ABSTRACT:
According to this invention, a semiconductor memory device includes N M-port RAMs (where each of M and N is a positive integer of not less than two), a data input terminal, N.times.(M-1) read address terminals, a write address terminal, and N.times.(M-1) data output terminals. The N M-port RAMs are operated in synchronization with a common clock signal. The data input terminal commonly inputs write data to data input terminals of the M-port RAMs. The N.times.(M-1) read address terminals independently input read addresses to first to (M-1)th port address terminals of the M-port RAMs. The write address terminal commonly inputs a write address to Mth port address terminals of the M-port RAMs. The N.times.(M-1) data output terminals independently output read data from data output terminals of the M-port RAMs.

REFERENCES:
patent: 4616310 (1986-10-01), Dill et al.
patent: 4893279 (1990-01-01), Rahman et al.
"Reconfigurable single/dual port RAM system", IBM TDB, vol. 29, No. 4, Sep. 1986, pp. 1881-1882.

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