Semiconductor memory device employing ferroelectric memory cell,

Static information storage and retrieval – Systems using particular element – Ferroelectric

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365222, G11C 700

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active

059699817

ABSTRACT:
A memory cell array of a semiconductor memory device is split into memory blocks. A DRAM
onvolatile mode switching circuit makes each memory cell operate similarly to a DRAM when each memory block is accessed from the exterior while making each memory cell operate as a nonvolatile memory cell to require no refreshment when each memory block is not accessed for a constant period. An internal timer circuit manages a waiting time for the memory block shifting to a nonvolatile mode after entering a non-accessed state. Thus, the semiconductor memory device can attain stable power consumption reduction hardly influenced by a user state.

REFERENCES:
"Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors", K. Takeuchi et al., IEICE Trans. Electron., vol. E79-C, No. 2, Feb. 1996, pp. 234-242.

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