Semiconductor memory device, controller, and read/write...

Details Semiconductor memory device, controller, and read/write... Semiconductor memory device, controller, and read/write...

2007-03-01

2009-12-15

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S230030

Reexamination Certificate

active

07633817

ABSTRACT:
A controller102and four flash memories F0to F3are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

REFERENCES:
patent: 4418394 (1983-11-01), Tai
patent: 5572466 (1996-11-01), Sukegawa
patent: 2007/0214309 (2007-09-01), Matsuura et al.
patent: 48-66745 (1973-09-01), None
patent: 5-020181 (1993-01-01), None
patent: 6-119128 (1994-04-01), None
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patent: 10-187359 (1998-07-01), None

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