Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-04-26
2003-10-14
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S229000
Reexamination Certificate
active
06633505
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of internal signals required for the respective operation modes by required minimum control, a control method thereof, and a control method of a semiconductor device.
2. Description of Related Art
Conventionally, irrespective of synchronous type/asynchronous type, a semiconductor memory for memorizing data by storing an electric charge in a cell capacitor, such as a dynamic random access memory (hereinafter abbreviated to a DRAM), has a refresh operation mode in addition to an ordinary data-input/output operation mode. These operations have, as one unit, a so-called operation cycle in which on the basis of an external command etc., an access operation to a memory cell, such as an input/output operation of data or a refresh operation, is carried out from a stand-by state, and is again returned to the stand-by state. Setting of the operation mode has been carried out for every operation cycle to determine what access operation is to be carried out in each of the operation cycles.
In the refresh mode, it is necessary to repeatedly refresh all memory cells in the DRAM successively within a predetermined time. Then, it is common to continuously carry out the refresh operation in a period when the ordinary data-input/output mode is not in action. By a so-called self-refresh mode, in each cycle from the entry of a self-refresh command to the exit in the synchronous type DRAM, or in the set period of CAS before RAS in the asynchronous type DRAM, the refresh operation is successively carried out for the respective memory cells while an internal address is switched. Since the operation mode is fixed to the refresh mode in this period, the operation mode for each operation cycle is not confirmed, and direct transition of the address of the memory cell as an object to be refreshed is carried out without going through an intermediate state such as a reset of address content outputted from the internal address between the operation cycles.
In recent years, with the spread of portable equipment, the functions demanded for the equipment are increased, and consequently, instead of a conventionally mounted static random access memory (hereinafter abbreviated to an SRAM), a memory of further large capacity has been demanded. Then, a DRAM having a built-in refresh function, a so-called pseudo-SRAM has been used, which uses a highly integrated DRAM memory cell as compared with an SRAM memory cell and has a built-in control concerning the refresh operation peculiar to the DRAM memory cell, so that an external control circuit such as a refresh controller is made unnecessary and the external specification is equivalent to the SRAM.
The pseudo-SRAM is automatically shifted to the refresh mode at any time as the need arises, and can carry out the refresh operation. Thus, in both the refresh mode of the internal control and the ordinary data-input/output mode of the external control, the operation requests are made at arbitrary timings, and synchronization can not be established between both the operation modes. Accordingly, the pseudo-SRAM cannot adopt the continuous refresh operation in which the direct transition of the inner address is carried out without confirming the operation mode for each operation cycle, and differently from the normal DRAM, it is necessary to discriminate the operation mode for each operation cycle. Thus, it is necessary to switch the state of the internal address into a specified state for each operation cycle.
Specifically, for example, in the case where the ordinary data-input/output mode of the external control is set as the basic operation mode, each time the operation cycle of the refresh mode is ended, the setting of the internal address is switched to the external address required in the ordinary data-input/output mode. Besides, if such an architecture is adopted that an intermediate reset state is set between operation cycles, the internal address is switched to the reset state each time the operation cycle of the refresh mode is ended.
FIG. 15
shows operational waveforms expressing address switching for each operation cycle concerning the pseudo-SRAM in which the ordinary data-input/output mode is set as the basic operation mode. A period in which a refresh operation requesting signal REQ (Ref) is selected is an operation period Ref of a refresh mode, and a refresh address ADD (Ref) generated in an internal address counter or the like is propagated to an internal address ADD (Int). Besides, a period in which a data-input/output requesting signal REQ (R/W) is selected, is an operation period R/W of a data input/output mode in which read/write of data is carried out, and an external address ADD (R/W) inputted from the outside is propagated to the internal address ADD (Int).
Besides, in the operation periods Ref and R/W of the refresh mode and the ordinary data-input/output mode respectively, it is necessary to select a memory cell block as a unit of memory cell activation. Since the memory cells are arranged in a matrix form, as signals for selecting the memory cell block, the signals for selecting the respective directions of a row direction and a column direction are needed. One signal of those is a block selecting signal CBx (x=0 to n). The number of the memory cell blocks selected by this signal CBx (x=0 to n) becomes a less selection number at the time of the ordinary data-input/output mode in which the input/output of data from/to the outside exists and it is desired to perform an operation at a required minimum consumed electric current, as compared with the time of the refresh mode in which a refresh period is regulated from the data holding characteristic. In
FIG. 15
, at the time of the ordinary data-input/output mode, one block selecting signal CBa or CBb is activated. On the other hand, at the time of the refresh mode, all the block selecting signals CBx (x=0 to n) are activated.
In
FIG. 15
, since the ordinary data-input/output mode is made the basic operation mode, at the time of the end of the operation period Ref of the refresh mode, the settings of the internal address ADD (Int) and the cell block selecting signal CBx (x=0 to n) become the external address ADD (R/W) of the ordinary data-input/output mode and the cell block selecting signal CBa or CBb.
In the above, the pseudo-SRAM is used as an example, and the description has been given of, as an example, the case where the address is switched between the internal address and the external address for each of two different operation modes of the refresh mode of the internal control and the data-input/output mode of the external control. Also in other semiconductor devices, there is a case where switching of an internal state typified by address switching at every operation mode is carried out.
However, in the conventional pseudo-SRAM, even if a next operation cycle subsequent to the refresh mode is the ordinary data-input/output mode, as the internal address ADD (Int) in the stand-by period SBY between these, as indicated by a region (A) of
FIG. 15
, there is a fear that an address value (B
1
or B
2
) of an unnecessary external address ADD (R/W) is set. At this time, the switching operation from the address value (A
1
or A
4
) of the refresh address ADD (Ref) to the unnecessary address value (B
1
or B
2
), and the switching operation from the unnecessary address value (B
1
or B
2
) to the address value (B
2
or B
3
) at the time of the ordinary data-input/output mode are unnecessary operations, and unnecessary electric current consumption is caused, which is problematic.
Such connection switching to the internal address ADD (Int) arises also in an operation state like a region (B) of
FIG. 15
in which the refresh mode continues over a plurality of operation cycles. In this case, since the operation of the refresh mode continues a
Fujitsu Limited
Phung Anh
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