Semiconductor memory device, control method therefor, and...

Details Semiconductor memory device, control method therefor, and... Semiconductor memory device, control method therefor, and...

2011-05-10

2011-05-10

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S196000, C365S230010, C365S222000, C365S230060, C365S189040

Reexamination Certificate

active

07940583

ABSTRACT:
There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

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Yoshiro Riho et al., USPTO Office Action, 12/320,891, Nov. 19, 2010, 16 pages.

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