Semiconductor memory device configured with I/O separation

Details Semiconductor memory device configured with I/O separation Semiconductor memory device configured with I/O separation

1999-12-17

2000-10-24

Phan, Trong

Static information storage and retrieval

Read/write circuit

Differential sensing

36523003, 36523008, G11C 702, G11C 800

Patent

active

061377406

ABSTRACT:
A common line shared by the sources of the transistors configuring a read gate is arranged in a sense amplifier region. A voltage control circuit is arranged at an intersection of the sense amplifier region and a subordinate decoder region. The voltage control circuit supplies to the common line a ground voltage in reading data and a voltage higher than the ground voltage in writing data. As such, erroneous read operation or current leakage does not occur when a read column select gate turns on in writing data.

REFERENCES:
patent: 5321646 (1994-06-01), Tomishima et al.
patent: 5724291 (1998-03-01), Matano
"Ultra LSI Memory", K. Ito, Advanced Electronics Series, Nov. 5, 1994, pp. 165-167.

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