Semiconductor memory device comprising programmable redundancy c

Details Semiconductor memory device comprising programmable redundancy c Semiconductor memory device comprising programmable redundancy c

1988-03-02

1989-06-13

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 700

Patent

active

048398640

ABSTRACT:
A semiconductor memory device comprises a plurality of memory cells arranged in a plurality of rows and columns, a plurality of row decoders for selecting one row of the plurality of rows, spare memory cells arranged in one row and a spare decoder for selecting the spare memory cells arranged in the one row. Each of the row decoders comprises a link element which can be melted by a laser beam. A plurality of decoder state determining logical circuits are provided corresponding to the plurality of row decoders. If and when a defective memory cell exists of the memory cells arranged in one row corresponding to each of the row decoders, the link element in the row decoder is melted in advance. When the row decoder having the link element melted in advance is selected by address signals, a corresponding decoder state determining logical circuit generates an SEE signal. The spare decoder is selected in place of the row decoder by the SEE signal.

REFERENCES:
patent: 4494220 (1985-01-01), Dumbri et al.
patent: 4556975 (1985-12-01), Smith et al.
patent: 4635232 (1987-01-01), Iwahashi et al.
patent: 4641285 (1987-02-01), Sasaki et al.
patent: 4648075 (1987-03-01), Segawa et al.
patent: 4658379 (1987-04-01), Fujishima et al.
IEEE Journal of Solid-State Circuits: "A Low Power Sub 100ns 256K Bit Dynamic RAM", by S. Fujii et al., vol. SC-18, No. 5, Oct. 1983, pp. 441-446.

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