Semiconductor memory device clamping the overshoot and undershoo

Details Semiconductor memory device clamping the overshoot and undershoo Semiconductor memory device clamping the overshoot and undershoo

1998-03-23

1999-05-18

Mai, Son

Static information storage and retrieval

Read/write circuit

Including signal clamping

257355, G11C7/00

Patent

active

059056797

ABSTRACT:
An input signal applied to a terminal receiving an external signal (e.g. a data input/output terminal DQj) is transmitted by an input signal line. A p well formed in a main surface of a p substrate is electrically isolated from the p substrate by an n well and a triple n well. The p well and the n well receive a potential level of the signal input line. An n diffusion layer is formed in a main surface of the p well and receives an external power supply potential Vdd.

REFERENCES:
patent: 5181091 (1993-01-01), Harrington, III et al.
patent: 5235201 (1993-08-01), Honna
patent: 5349227 (1994-09-01), Murayama
patent: 5581103 (1996-12-01), Mizukami
patent: 5708610 (1998-01-01), Okasaka et al.

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