Semiconductor memory device capable of through rate control of e

Details Semiconductor memory device capable of through rate control of e Semiconductor memory device capable of through rate control of e

1997-07-21

1999-03-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365191, 36518901, G11C 700

Patent

active

058869344

ABSTRACT:
A semiconductor memory device comprises first and second data buses. An output drive circuit adjusts the potentials at the first and second data buses in response to an internal read signal read from a memory cell. The gates of a PMOS transistor and an NMOS transistor forming an output stage corresponding to an output final stage are connected to ends of the first and second data buses, respectively. The potential of an output signal derived from the output stage loosely transits with a value decided by the capacitances of the first and second data buses. Thus, through rate control of the output signal can be implemented without reducing current drivability of the MOS transistors forming the output final stage.

REFERENCES:
patent: 4890016 (1989-12-01), Tanaka et al.
patent: 5140194 (1992-08-01), Okitaka
patent: 5371705 (1994-12-01), Nakayama
patent: 5473565 (1995-12-01), Kusakari
patent: 5500820 (1996-03-01), Nakaoka
"A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", T. Wada et al., IEEE Journal of Solid-State Circuits, vol. sc-22, No. 5, Oct. 1987 pp. 727-732.

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