Semiconductor memory device capable of testing memory cells...

Details Semiconductor memory device capable of testing memory cells... Semiconductor memory device capable of testing memory cells...

2008-07-29

2008-07-29

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S710000, C365S201000

Reexamination Certificate

active

07406637

ABSTRACT:
A semiconductor memory device comprises a memory core, data control circuit, flag register, data register and computation circuit. The memory core has a plurality of memory cells for storing data. The data control circuit writes and reads first test data to and from the memory cells in synchrony with a clock signal. The flag register stores a plurality of flag data items. The data register stores second test data input corresponding to input of a command. The computation circuit performs, at every cycle, computation of the second test data, stored in the data register, and each of the flag data items stored in the flag register, thereby generating the first test data, until an n-th (n is a positive integer) cycle of the clock signal is reached. The first test data is written to the memory cells by the data control circuit.

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Wohl et al. “Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture,” 40th Design Automation Conference pp. 566-575 (2003).

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