Semiconductor memory device capable of stably performing...

Details Semiconductor memory device capable of stably performing... Semiconductor memory device capable of stably performing...

2006-01-24

2006-01-24

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S233500

Reexamination Certificate

active

06990032

ABSTRACT:
A semiconductor memory device includes a clock enable signal self refresh buffer for generating a self refresh clock enable signal by receiving the clock enable signal in the self refresh mode, an internal clock signal generating unit for generating an internal clock signal by receiving the external clock signal, a signal synchronization unit for generating an internal clock enable signal by synchronizing the clock enable signal with the internal clock signal, a level detection unit for generating a level detection signal by detecting levels of the internal clock enable signal and the self refresh clock enable signal, a clock self refresh buffer for receiving the external clock signal during a self refresh mode in response to the level detection signal, and a self refresh command generation unit for activating a self refresh command in response to the level detection signal and inactivating the self refresh command in response to the level detection signal and an output signal of the clock self refresh buffer.

REFERENCES:
patent: 6333886 (2001-12-01), Cho et al.
patent: 6912169 (2005-06-01), Choi
patent: 2004/0240296 (2004-12-01), Jeong

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