Semiconductor memory device capable of stable sensing operation

Details Semiconductor memory device capable of stable sensing operation Semiconductor memory device capable of stable sensing operation

2001-01-08

2001-11-06

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S205000, C365S226000

Reexamination Certificate

active

06314028

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a dynamic semiconductor memory device with a sense amplifier circuit that differentially amplifies data in memory cells. More particularly, the present invention relates to a structure of a sense power supply circuit generating a power supply voltage of a sense amplifier circuit.
2. Description of the Background Art
In accordance with the development of recent computers and information processing terminals, the demand placed on devices employed as the main storage in these equipment has become higher. More specifically, there is an increasing not only for large storage capacity, but also for increasing the effective data transfer rate and lowering power consumption to allow usage of a large storage capacity memory in portable apparatuses. As to a DRAM (dynamic random access memory) widely used as the main memory device, a SDRAM that carries out data input/output in synchronization with clock signals (clock synchronous type DRAM), a DDR (double data rate) SDRAM that carries out data input/output in synchronization with both the rising and falling edges of clock signals, and the like, typical of a DRAM that allows data to be transferred at high speed, are beginning to be employed widely.
In a DRAM, information is stored in the form of electrical charges in a capacitor of a memory cell. Since data of a H (high) level written into a DRAM cell will be naturally lost by leakage current when left intact, a data re-write operation called “refresh” must be carried out periodically.
In recent DRAMs, an operation called self refresh is defined by specification. In a self refresh operation mode, a refresh timing is set automatically by a timer provided in the DRAM. A refresh operation is carried out automatically at the set refresh timing. The self refresh operation is carried out during a standby state in which the DRAM is not accessed. By suppressing the self refresh current consumed during this self refresh operation, the current consumption of the DRAM can be reduced to increase the continuous operative period of time of, for example, portable communication information terminals (by virtue of increase of the battery lifetime).
The basic factors determining the value of the self refresh current depend on the bit line potential amplitude, the bit line load and the refresh cycle. The refresh cycle is closely related to the data retaining ability of the memory cell. A longer refresh cycle can be set as the data retaining ability of the memory cell becomes higher. As a method of increasing the memory cell data retaining ability on a circuit basis, Asakura et al. has proposed the BSG (boosted sense ground) scheme. This BSG scheme is described in details in, for example, IEEE Journal of Solid-State Circuits 1994, pp.1303-1309. The principle of the BSG scheme will described in the following.
FIG. 35
represents a structure of a memory cell array in a DRAM with the conventional BSG scheme. Referring to
FIG. 35
, the DRAM includes memory cells MC arranged in a matrix of rows and columns, a pair of bit lines BL and ZBL arranged corresponding to each column, and a word line WL arranged corresponding to each row of memory cells MC. In
FIG. 35
, one memory cell MC is depicted as a representative. Memory cell MC includes a memory cell capacitor Cs to store information, and an access transistor MT formed of an N channel MOS transistor (insulation gate field effect transistor) and rendered conductive in response to a signal voltage on word line WL to connect memory cell capacitor Cs to bit line BL. Each of bit lines BL and ZBL has a parasitic capacitance (bit line capacitance) Cb.
Bit lines BL and ZBL are provided with a bit line equalize/precharge circuit E/P precharging and equalizing bit lines BL and ZBL to an intermediate voltage Vble in response to a bit line equalize designation signal BLEQ, and a sense amplifier circuit S/A amplifying the voltage difference of bit lines BL and ZBL in response to sense amplifier activation signals SON and ZSOP.
Bit line equalize/precharge circuit E/P includes precharge transistors TQ
7
and TQ
8
transmitting intermediate voltage Vble to respective bit lines BL and ZBL in response to bit line equalize designation signal BLEQ, and an equalize transistor TQ
9
electrically short-circuiting bit lines BL and /BL in response to bit line equalize designation signal BLEQ. Transistors TQ
7
-TQ
9
are formed of N channel MOS transistors. Intermediate voltage Vble is equal to the voltage level of the intermediate value between a sense power supply voltage Vdds and a voltage Vbsg higher than ground voltage GND, i.e. (Vdds+Vbsg)/2.
Sense amplifier circuit S/A includes an N sense amplifier rendered active, when sense amplifier activation signal SON is active, to discharge one of bit lines BL and /BL of the lower potential, and a P sense amplifier rendered active, when sense amplifier activation signal ZSOP is active, to charge another of bit lines BL and /BL of the higher potential. The N sense amplifier includes: an N channel MOS transistor TQ
1
having a drain connected to bit line BL and a gate connected to bit line /BL, an N channel MOS transistor TQ
2
having a drain connected to bit line /BL and a gate connected to bit line BL, and an N channel MOS transistor TQ
3
rendered conductive, when sense amplifier activation signal SON is active, to transmit sense power source voltage Vsan (=Vbsg) to the sources of MOS transistors TQ
1
and TQ
2
. In the BSG scheme, sense power source voltage Vsan is set to the level of a boosted voltage Vbsg higher than ground voltage GND.
The P sense amplifier includes a P channel MOS transistor TQ
4
having a drain connected to bit line BL and a gate connected to bit line /BL, a P channel MOS transistor TQ
5
having a drain connected to bit line /BL and a gate connected to bit line BL, and a P channel MOS transistor TQ
6
rendered conductive when sense amplifier activation signal ZSOP is active to transmit sense power supply voltage Vsap to the sources of MOS transistors TQ
4
and TQ
5
. Sense power supply voltage Vsap corresponds to the level of sense power supply voltage Vdds. The refresh operation of memory cell MC will now be described with reference to the signal waveform diagram of FIG.
36
.
In a standby state, sense amplifier activation signal SON is at an L level of ground voltage GND, and sense amplifier activation signal ZSOP is at an H level of sense power supply voltage Vdds. Sense amplifier circuit S/A is in an inactive state. Bit line equalize designation signal BLEQ is at an active state of an H level. MOS transistors TQ
7
-TQ
9
included in bit line equalize/precharge circuit E/P all stay in a conductive state. Bit lines BL and /BL are precharged and equalized to the level of intermediate voltage Vble. Word line WL is at the level of ground voltage GND. Access transistor MT of memory cell MC maintains a non-conductive state.
Upon access to a memory cell (starting of a refresh cycle), bit line equalize designation signal BLEQ is pulled down to an L level. Bit line equalize/precharge circuit E/P is rendered inactive. Bit lines BL and ZBL attain a floating state at the level of intermediate voltage Vble.
By a row select circuit not shown, word line WL is driven to a selected state according to an address signal, whereby the voltage level of word line WL rises. When the voltage level of word line WL becomes higher than the voltage level of bit line BL by the threshold voltage of the access transistor, access transistor MT is rendered conductive, whereby charge is transferred between bit line BL and memory cell capacitor Cs.
FIG. 36
represents an operation waveform when memory cell MC stores data of an H level, and the voltage level of bit line BL rises.
Since bit line ZBL does not have a memory cell connected thereto, bit line ZBL maintains the level of intermediate voltage Vble.
When the voltage difference between bit lines BL and ZBL becomes large enough, sense amplifier activat

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