Semiconductor memory device capable of simultaneously designatin

Details Semiconductor memory device capable of simultaneously designatin Semiconductor memory device capable of simultaneously designatin

1996-01-31

1998-08-11

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365193, G11C 700

Patent

active

057936854

ABSTRACT:
The semiconductor device includes a state detection circuit receiving control signals address signals and row address signals for outputting timing detection signals and test group detection signals, and a test mode setting signal generating circuit receiving row address signals, timing detection signals and test group detection signals for outputting multibit test mode setting signal and test mode setting signals accordingly. The semiconductor device allows setting of standardized multibit test mode singly, and also allows simultaneous setting of the multibit test mode and a special test mode not standardized by the Joint Electron Device Engineering Council, so that the standard is satisfied and the time for special tests not standardized can be reduced.

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Joseph Neal et al, A 1Mb CMOS DRAM with Design-for-Test Functions, IEEE International Solid-State Circuits Conference, Feb. 21, 1986, pp. 264-265.
German Office Action dated Apr. 18, 1997 and English translation thereof.

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