Semiconductor memory device capable of simultaneously...

Details Semiconductor memory device capable of simultaneously... Semiconductor memory device capable of simultaneously...

2005-07-26

2005-07-26

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C714S006130

Reexamination Certificate

active

06922750

ABSTRACT:
A semiconductor memory device is capable of simultaneously reading data and refreshing data and checking whether a data restoring function is operating normally. A data inputting circuit receives data inputted from an external circuit. A parity generating circuit generates parity data from the data input from the data inputting circuit. A memory stores the data input from the data inputting circuit and the parity data generated by the parity generating circuit. A refreshing circuit refreshes the memory. A reading circuit reads the data from the memory. A restoring circuit restores data to be refreshed by the refreshing circuit from other data read normally and corresponding parity data, while the reading circuit is reading data. A data outputting circuit outputs the data read by the reading circuit and the data restored by the restoring circuit. A parity outputting circuit directly reads and outputs the parity data stored in the memory.

REFERENCES:
patent: 4766573 (1988-08-01), Takemae
patent: 5297102 (1994-03-01), Tanizaki
patent: 6108229 (2000-08-01), Shau
patent: 6421292 (2002-07-01), Kitamoto et al.
patent: 6529435 (2003-03-01), Yagishita et al.
patent: 2000-368423 (2000-04-01), None

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