Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-05-06
1998-10-13
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, 36518902, 36518905, 36518907, 36518908, 365222, 3652257, 365227, 365228, G11C 2900
Patent
active
058222570
ABSTRACT:
A memory device has a plurality of word lines, a plurality of bit lines crossing the word lines, and a memory cell array having memory cells disposed at respective points of intersection between the word lines and the bit lines. The memory device includes a first redundant memory cell array, a first address comparison circuit, a second redundant memory cell array, and a second address comparison circuit. The first redundant memory cell array replaces memory cells with redundant memory cells per bit or a small number of bits. The first address comparison circuit stores an addresses of memory cells to be replaced, compares the stored addresses with an inputted address, and allows a memory cell to be replaced effectively with a redundant memory cell in the first redundant memory cell array when a stored address matches the inputted address. The second redundant memory cell array replaces memory cells with redundant memory cells per word line or bit line. The second address comparison circuit stores addresses corresponding to word lines or bit lines to be replaced, compares the stored addresses with an inputted address, and allows memory cells to be replaced effectively with redundant memory cells in the second redundant memory cell array when a stored address matches the inputted address.
REFERENCES:
patent: 5157634 (1992-10-01), Dhong et al.
Fujitsu Limited
Nguyen Viet Q.
Tran Andrew Q.
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