Semiconductor memory device capable of relieving defective cell

Details Semiconductor memory device capable of relieving defective cell Semiconductor memory device capable of relieving defective cell

2005-01-25

2005-01-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189030, C365S189050, C365S189110, C365S189120, C365S230030, C365S230060, C365S207000, C711S105000

Reexamination Certificate

active

06847564

ABSTRACT:
A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

REFERENCES:
patent: 6201744 (2001-03-01), Takahashi
patent: 6269033 (2001-07-01), Ishida et al.
patent: 6272056 (2001-08-01), Ooishi
patent: 6519192 (2003-02-01), Ooishi
Toshimasa Namekawa et al., “Dynamically Shift-Switched Dataline Redundancy Suitable for DRAM Macro with Wide Data Bus”, IEEE Journal of Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 705-712.
T. Namekawa, et al., Symposium on VLSI Circuits Digest of Technical Papers, pp. 149-152, “Dynamically Shift-Switched Dataline Redundancy Suitable for DRAM Macro with Wide Data Bus”, 1999.

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