Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-09-12
2010-11-16
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C714S710000, C714S711000
Reexamination Certificate
active
07835206
ABSTRACT:
A semiconductor memory device includes plural banks, defect relief circuits individually provided for these banks, a defective-address storing circuit that stores defective addresses, and a comparing circuit that compares an access-requested address with a defective address. The defective-address storing circuit and the comparing circuit are allocated in common to two banks, respectively. With this arrangement, a chip area can be decreased.
REFERENCES:
patent: 6055196 (2000-04-01), Takai
patent: 2002/0141264 (2002-10-01), Mori et al.
patent: 10-334690 (1998-12-01), None
patent: 2004-158069 (2004-06-01), None
patent: 2006-108394 (2006-04-01), None
Elpida Memory Inc.
Hur J. H.
Scully , Scott, Murphy & Presser, P.C.
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