Semiconductor memory device capable of reducing leakage...

Details Semiconductor memory device capable of reducing leakage... Semiconductor memory device capable of reducing leakage...

2001-11-14

2002-06-25

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C365S189020, C365S189070, C365S189090

Reexamination Certificate

active

06411560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device with plural power supply voltages at respective different voltage levels, capable of reducing a leakage current flowing into a substrate.
2. Description of the Background Art
Attention has been focused on DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) and so on as a memory capable of inputting/outputting data at high speed.
Referring to
FIG. 33
, a prior art semiconductor memory device
1000
includes: memory cells
1001
and
1002
; a sense amplifier
1010
; a gate circuit
1020
; peripheral circuit
1030
; and a bit line driver
1070
. Note that
FIG. 33
shows only a part of semiconductor memory device
1000
since the figure is to describe fundamental operation of semiconductor memory device
1000
.
Memory cell
1001
is connected to a bit line BL and a word line W
1
. Memory cell
1002
is connected to a bit line /BL and a word line W
2
. When word line W
1
is activated, memory cell
1001
outputs data onto bit line BL or data is inputted to memory cell
1001
from bit line BL. When word line W
2
is activated, memory cell
1002
outputs data onto bit line /BL or data is inputted to memory cell
1002
from bit line /BL.
Sense amplifier
1010
includes P channel MOS transistors
1011
to
1013
; and N channel MOS transistors
1014
to
1016
. P channel NOS transistor
1011
is connected between a power supply node
1017
and a node
1031
and receives a sense amplifier activation signal /SE at the gate terminal thereof. P channel MOS transistor
1012
and N channel MOS transistor
1014
are connected in series between nodes
1031
and
1032
. P channel MOS transistor
1013
and N channel MOS transistor
1015
are connected in series between nodes
1031
and
1032
. P channel MOS transistor
1012
and N channel MOS transistor
1014
in series connection are connected in parallel to P channel MOS transistor
1013
and N channel MOS transistor
1015
in series connection. N channel MOS transistor
1016
is connected between node
1032
and a ground node
1018
and receives a sense amplifier activation signal SE at the gate terminal thereof.
A node
1033
is connected to bit line BL. A node
1034
is connected to bit line /BL. P channel MOS transistor
1012
and N channel MOS transistor
1014
receive a voltage on bit line BL at the gate terminals thereof. P channel MOS transistor
1013
and N channel MOS transistor
1015
receive a voltage on bit line /BL at the gate terminals thereof. An array power supply voltage VccA is supplied onto power supply node
1017
and ground voltage is supplied onto ground node
1018
.
When word line W
1
is activated and data [
1
] is read out from memory cell
1001
, the voltage on bit line BL comes to be voltage VccA/
2
+&agr; slightly higher than a precharge voltage VccA/
2
and bit line /BL assumes a precharge voltage VccA/
2
. In such a state, sense amplifier activation signal SE at H (logical high) level is inputted to sense amplifier
1010
. Thereby, sense amplifier
1010
is activated. Voltage VccA/
2
+&agr; is transmitted along bit line BL and applied onto the gate terminals of P channel MOS transistor
1012
and N channel MOS transistor
1014
. Then, P channel MOS transistor
1012
is turned off, while N channel MOS transistor
1014
is turned on, with the result that a voltage on node
1034
is lowered to ground voltage (0 V) and in turn, a voltage on bit line /BL comes to 0 V.
Since a voltage on bit line /BL is applied to the gate terminals of P channel MOS transistor
1013
and N channel MOS transistor
1015
, P channel MOS transistor
1013
is turned on, while N channel MOS transistor
1015
is turned off to cause a voltage on node
1033
to be array power supply voltage VccA. Then, a voltage on bit line BL becomes array power supply voltage VccA. In such operation, voltages on bit lines BL and /BL showing data [
1
] read out from memory cell
1001
are amplified from (VccA/
2
+&agr;, VccA/
2
) to (VccA,
0
), respectively.
When data [
0
] is read out from memory cell
1001
, a voltage on bit line BL becomes a voltage VccA/
2
−&agr; slightly lower than precharge voltage VccA/
2
, and a voltage on bit line /BL becomes precharge voltage VccA/
2
. Voltage VccA/
2
is transmitted along bit line /BL and applied onto the gate terminals of P channel MOS transistor
1013
and N channel MOS transistor
1015
of sense amplifier
1010
. Then, P channel MOS transistor
1013
is turned off, while N channel MOS transistor
1015
is turned on to cause a voltage on node
1033
to be ground voltage (0V). Thus, a voltage on bit line BL becomes 0 V.
Since a voltage on bit line BL is applied onto the gate terminals of P channel MOS transistor
1012
and N channel MOS transistor
1014
, P channel MOS transistor
1012
is turned on, while N channel MOS transistor
1014
is turned off to cause a voltage on node
1034
to be array power supply voltage VccA. Then, a voltage on bit line /BL becomes array power supply voltage VccA. In such operation, voltages on bit lines BL and /BL showing data [
0
] read out from memory cell
1001
are amplified from (VccA/
2
−&agr;, VccA/
2
) to (
0
, VccA), respectively.
When data is read out from memory cell
1002
, as well, sense amplifier
1010
amplifies voltages on bit lines BL and /BL performing the above operation.
When data is written onto memory cells
1001
and
1002
, sense amplifier
1010
transfers voltages transmitted from a global data line pair GIO and /GIO as VccA and
0
(or
0
and VccA) onto bit line pair BL and /BL, respectively.
Therefore, sense amplifier
1010
amplifies data read out from memory cells
1001
and
1002
using a cross-coupled latch, or alternatively transfers data written from outside semiconductor memory device
1000
onto bit lines BL and /BL using the cross-coupled latch.
Gate circuit
1020
includes N channel MOS transistors
1021
and
1022
. N channel MOS transistor
1021
is connected to bit line BL at the drain terminal thereof and to global data line GIO at the source terminal, and receives a column select signal VACSL at the gate terminal thereof. N channel MOS transistor
1022
is connected to bit line /BL at the drain terminal thereof and to global data line /GIO at the source terminal, and receives column select signal VACSL at the gate terminal thereof. Therefore, N channel MOS transistor
1021
is turned on when receiving column select signal VACSL at H level at the gate terminal thereof to connect global data line GIO to bit line BL. N channel MOS transistor
1022
is turned on when receiving column select signal VACSL at the gate terminal thereof to connect global data line /GIO to bit line /BL.
Peripheral circuit
1030
includes: a GIO line write driver
1040
; a read amplifier
1050
; and a GIO line equalize circuit
1060
. GIO line write driver
1040
includes: inverters
1041
and
1044
to
1047
; NAND gates
1042
and
1043
; P channel MOS transistors
1048
and
1051
; and N channel MOS transistors
1049
and
1052
. Inverter
1041
inverts a signal inputted at terminal
1028
to output the inverted input to one terminal of NAND gate
1043
. NAND gate
1042
receives a signal inputted at terminals
1028
and
1029
to invert a logical product of the received two signals and output the inverted logical product as a signal. NAND gate
1043
receives an output signal of inverter
1041
and a signal inputted at terminal
1029
to invert a logical product of the received two signals and output the inverted logical product as a signal. Inverter
1044
inverts an output signal of NAND gate
1042
. Inverter
1045
inverts an output signal of NAND gate
1043
. Inverter
1046
inverts an output signal of inverter
1044
. Inverter
1047
inverts an output signal of inverter
1045
.
P channel MOS transistor
1048
and N channel MOS transistor
1049
are connected in series between a power supply node
1053
and

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of reducing leakage... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of reducing leakage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of reducing leakage... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2890982