Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-06-18
1998-07-07
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
36518907, 365240, 36523003, 36518903, 371 212, G11C 2900
Patent
active
057779333
ABSTRACT:
A compression reading switch circuit is provided between a data equality/inequality determination circuit and compressed one data input/output terminal in a DRAM. In the I/O compression mode, desired data can be read out among output data DOT from the determination circuit and read data D01-D04 thereby specifying a defective memory cell among four memory cells.
REFERENCES:
patent: 5579272 (1996-11-01), Uchida
Akamatsu Hiroshi
Horihata Shuichi
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
Tran Andrew Q.
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