Semiconductor memory device capable of reading information store

Details Semiconductor memory device capable of reading information store Semiconductor memory device capable of reading information store

1996-03-28

1997-10-21

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

056803540

ABSTRACT:
A defective bit address registering circuit stores an address corresponding to a detective memory cell replaced with a redundant memory cell in a non-volatile manner, and activates a redundant memory cell selection signal S2 if an internal address signal A0, . . . , An, /A0, . . . , /An matches a defective bit address. An I/O data inverting circuit receives input data and output data and outputs the received data without inversion if the redundant memory cell selection signal S2 is inactive. On the other hand, the I/O data inverting circuit outputs inverted data of the received data if the redundant memory cell selection signal S2 is active. Accordingly, if a read operation is performed when data in all the memory cells are at an "L" level such as right after the power supply is turned on, a signal at an "H" level is output only when a memory cell corresponding to a defective bit address is accessed.

REFERENCES:
patent: 4480199 (1984-10-01), Varshney et al.
patent: 4984205 (1991-01-01), Suugibayashi
patent: 5128944 (1992-07-01), Flaherty
patent: 5206831 (1993-04-01), Wakamatsu

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