Semiconductor memory device capable of preventing...

Details Semiconductor memory device capable of preventing... Semiconductor memory device capable of preventing...

2000-07-13

2001-05-08

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S233100

Reexamination Certificate

active

06229756

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-28206, filed on Jul. 13, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a circuit for controlling a column selection line in a semiconductor memory device.
In semiconductor memory devices, and dynamic random access memories (DRAMs) in particular, as the level of integration increases, internal signal lines become longer, and their load increases accordingly. When the load of column address lines, which are internal signal lines, greatly increases, the operation speed of the device may slow down or current consumption may increase.
FIG. 1
is a block diagram schematically illustrating a conventional DRAM. Referring to
FIG. 1
, the conventional DRAM includes an address buffer
11
, a column address decoder
12
, a column selection line control signal generator
15
, and a column selection line driver
13
, and a memory cell array
14
.
The address buffer
11
buffers externally-applied addresses A
0
through A
13
and provides column addresses CA
0
through CA
9
, CA
12
, and CA
13
. The column address decoder
12
receives the column addresses CA
0
through CA
9
, CA,
12
, and CA
13
, and decodes them into first and second decoded column addresses FDCA
i
and SDCA
i
. The column selection line control signal generator
15
receives the column addresses CA
12
and CA
13
and generates a column selection line control signal CSC in response to an internal clock signal ICLK. The column selection line driver
13
receives the first and second decoded addresses FDCA
i
and SDCA
i
(where i is an integer) of the column address decoder
12
and drives column selection lines CSL
i
(where, i is an integer) in response to the column selection line control signal CSC. These column selection lines CSL
i
are then provided to the memory cell array
14
.
CA
12
and CA
13
denote bank selection bits when the memory cell array
14
includes a plurality of banks. The first decoded column address FDCA
i
denotes signals obtained by decoding CA
0
through CA
2
in the column address decoder
12
, and the second decoded column address SDCA
i
denotes signals obtained by decoding CA
3
through CA
9
in the column address decoder
12
.
FIG. 2
is a circuit diagram of a unit circuit in the column selection line driver
13
shown in FIG.
1
.
FIG. 3
is a circuit diagram of the column selection line control signal generator
15
shown in FIG.
1
.
FIG. 4
is a timing diagram of the signals shown in FIG.
2
.
As described above, as the level of integration increases in a DRAM, the column address lines, which transmit the outputs of the address buffer
11
, i.e., the buffered column addresses CA
0
through CA
9
, CA
12
, and CA
13
, may be more greatly loaded. In addition, the loads of the column address lines may differ from one another.
For example, one of CA
i
(where i ranges from 0 to 9) may be delayed for a time t
1
with respect to CA
12
and CA
13
as shown in FIG.
4
. This may happen because of the difference between the loads of the column address lines.
FIG. 4
shows a case in which one among CA
3
through CA
9
is delayed for a period of t
1
.
Accordingly, in the conventional DRAM, one among the second decoded column addresses SDCA
i
, which are generated by CA
3
through CA
9
, i.e., SDCA
j
, has invalid data as indicated by the area a for a period of t
1
. Thus, one among the column selection lines CSL
i
, i.e., CSL
x
, is abnormally enabled in advance as indicated by the area b. As a result of this, two column selection lines are enabled simultaneously, which causes the DRAM to malfunction.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device that operates normally and is unaffected in its operating speed, even when column address lines for transmitting column addresses are greatly loaded and even when the loads on the column address lines are different from one another.
Accordingly, to achieve the above object, the present invention provides a semiconductor memory device including a memory cell array; a column selection line driver for receiving decoded addresses and driving column selection lines of the memory cell array in response to a column selection line control signal; a control signal generator for generating first and second control signals in response to an internal clock signal, an externally-input column address strobe signal, and an externally-input write enable signal; and a column selection line control signal generator for receiving first and second buffered column address data and generating the column selection line control signal in response to the internal clock signal and one of the first and second control signals.
The semiconductor memory device may comprise an address buffer for buffering externally-input column addresses and outputting the first and second buffered column address data; and a column address decoder for receiving and decoding the first and second buffered column address data and outputting the decoded addresses.
The internal clock signal preferably has a synchronous relationship with an externally-input system clock signal.
The first control signal is preferably generated in response to the column address strobe signal and the internal clock signal, and the second control signal is preferably generated in response to the write enable signal and the internal clock signal.
The column selection line control signal generator may comprise a NAND gate for selectively receiving the second buffered column address data and the inverted signals of the buffered column address data; a latch for latching the output of the NAND gate in response to the internal clock signal; and a logic unit for performing a logic operation with respect to the output of the latch and the first and second control signals, in response to the internal clock signal.
The first buffered column address data preferably includes the 0
th
through 9
th
bits of the column address, and the second buffered column address data includes the 12
th
and 13
th
bits of the column address.
The control signal generator may comprise a first inverter for inverting the column address strobe signal; a first switch for transferring the output of the first inverter in response to the internal clock signal; a first AND gate for performing an AND operation with respect to the internal clock signal and the output of the first switch, and outputting the result as the first control signal; a second inverter for inverting the write enable signal; a second switch for transferring the output of the second inverter in response to the internal clock signal; and a second AND gate for performing an AND operation with respect to the internal clock signal and the output of the second switch, and outputting the result as the second control signal.


REFERENCES:
patent: 6055207 (2000-04-01), Nam
patent: 6111795 (2000-08-01), Takita et al.

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