Semiconductor memory device capable of performing refresh operat

Details Semiconductor memory device capable of performing refresh operat Semiconductor memory device capable of performing refresh operat

1992-04-09

1993-10-12

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, G11C 1140

Patent

active

052532119

ABSTRACT:
The semiconductor memory device according to the present invention includes a plurality of memory cells each for holding information charge arranged in a matrix of rows and columns, a plurality of bit line pairs, a plurality of word lines, a plurality of sense amplifiers grounded corresponding to the bit line pairs for amplifying a potential difference appearing between the bit lines of each bit line pair when information charge of each memory cell is read by a reading circuit, a plurality of holding circuits each provided corresponding to each of the bit line pairs and connected to the corresponding bit lines for holding the amplified potential difference of each bit line pair, a plurality of transistors for disconnecting the holding circuits from the bit line pairs with each holding circuit holding the potential difference of each corresponding bit line pair, a refresh device for refreshing a memory cell with a transistor being turned off, and an output device for outputting the potential difference held by one of the holding circuits corresponding to the selected column.

REFERENCES:
patent: 4330852 (1982-05-01), Redwine
patent: 4914630 (1990-04-01), Fujishima et al.
"A 1-Mbit CMOS DRAM with Fast Page Mode and Static Column Mode", by Shozo Saito et al., IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 903-908.

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