Semiconductor memory device capable of performing internal test

Static information storage and retrieval – Read/write circuit – Testing

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Details

36518905, 36518907, G11C 2900

Patent

active

059264241

ABSTRACT:
The semiconductor memory device includes a data generation circuit and a tristate buffer portion. The data generation circuit generates test data in block units in accordance with a combination of signals received from an external pin. The tristate buffer portion directly writes the test data to an SRAM bit line. After the test data is written to a DRAM array, data corresponding to the test data is read. In a data comparison and determination circuit included in a data transfer buffer read data in block units is compared and determined. The determination results are collectively output to a signal line.

REFERENCES:
patent: 5535171 (1996-07-01), Kim et al.
patent: 5661729 (1997-08-01), Miyazaki et al.

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