Semiconductor memory device capable of performing burn-in...

Details Semiconductor memory device capable of performing burn-in... Semiconductor memory device capable of performing burn-in...

2002-08-20

2004-05-25

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S051000, C365S063000

Reexamination Certificate

active

06741510

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device capable of performing a burn-in test at high speed.
2. Description of the Background Art
As semiconductor memory devices storing data to a high capacity, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory) and others have been put into practical use.
The semiconductor memory devices are shipped after judgement on pass/fail. The judgement on pass/fail of a semiconductor memory device as fabricated is performed by actually inputting/outputting data to/from memory cells included in the device to confirm that write data and read data coincide with each other and by applying a stress thereto in burn-in.
In company with the recent advent of a high capacity semiconductor memory device, however, portions requiring a stress to be applied thereto increase, which causes a test time for burn-in to be longer, having lead to a problem of a high cost.
In order to solve such a problem, a technique is disclosed in Japanese Patent laying-Open No. 5-159568 that plural word lines are simultaneously selected in a burn-in test for application of a stress.
Furthermore, a technique is disclosed in Japanese Patent Laying-Open No. 2001-184897 that a burn-in test signal is inputted to a predecoder and signals for selecting plural word lines are generated by the predecoder to activate the plural word lines simultaneously for application of a burn-in stress.
Moreover, a technique is disclosed in Japanese Patent Laying-Open No. 2001-14892 that even-numbered word lines and odd-numbered word lines are selectively activated for application of a burn-in stress.
The prior art techniques disclosed in Japanese Patent Laying-Open Nos. 5-159568, 2001-184897 and 2001-14892 contribute to reduction in test time for burn-in, while more effective application of a stress in burn-in is not sufficiently achieved therewith. If an effective application of a stress in burn-in is intended with the prior art techniques, a necessity arises for more of inspection circuits in a semiconductor memory device, leading to a problem of increase in area thereof.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a semiconductor memory device capable of effectively applying a stress by a burn-in test.
According to an aspect of the present invention, a semiconductor memory device includes: a memory cell array; and a test circuit consecutively applying plural stresses to the memory cell array in response to a transition request to a burn-in test mode.
In the burn-in test, the plural stresses are consecutively applied to the memory cell array.
According to the present invention, therefore, a time for a burn-in test can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5400282 (1995-03-01), Suzuki et al.
patent: 5-159568 (1993-06-01), None
patent: 2001-14892 (2001-01-01), None
patent: 2001-184897 (2001-07-01), None

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