Semiconductor memory device capable of operating at high speed a

Details Semiconductor memory device capable of operating at high speed a Semiconductor memory device capable of operating at high speed a

1997-02-26

1998-06-30

Le, Vu A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 36523005, G11C 700

Patent

active

057743932

ABSTRACT:
A memory cell includes a read/write word line R/WL1 driving access transistor Q1 in read and write operations and a write word line WL1 driving access transistor Q2 in the write operation. In the write operation, both access transistors Q1 and Q2 are driven, and storage information is written in the memory cell by a bit line and a /bit line having potentials complementary to each other. On the other hand, in the read operation, only access transistor Q1 is rendered conductive, and storage information is read out through the bit line. Since access transistor Q2 is rendered non-conductive, a P type TFT transistor and an N type transistor operate as a CMOS type inverter having a large voltage gain. Therefore, a sufficient operating margin is secured even in the read operation.

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"An Asymmetric Memory Cell Using a C-TFT for ULSI SRAMs" 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39.
"A 16-Mb CMOS SRA with a 2.3um.sup.2 Single-Bit Line Memory Cell," IEE Journal of Solid-State Circuits, (vol. 28, No. 11, Nov. 1993), pp. 1125-1130.

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