Semiconductor memory device capable of multiple word-line...

Details Semiconductor memory device capable of multiple word-line... Semiconductor memory device capable of multiple word-line...

1999-11-18

2001-04-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230060, C365S230030

Reexamination Certificate

active

06215712

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device provided with test functions to test memory cells.
2. Description of the Related Art
Semiconductor memory devices such as DRAMs are subjected to inspections to check whether memory cells correctly function with regard to data storage capacity. Such inspections are conducted at a site of manufacturers before shipment of products. A test referred to as a disturb test activates a given word line, and writes data of either 0 or 1 in a memory cell. The word line is then deactivated, and surrounding word lines are switched back and forth between an active state and an inactive state. After this operation, the word line is activated again to check whether the data initially stored in the memory cell can be correctly read. This test can evaluate whether data of a given word line is affected when surrounding word lines are driven.
In conventional DRAMs, each bank is provided with one row-address-latch circuit, which latches a row address. When a given bank is activated, therefore, only one row address can be accessed in this bank. In this manner, conventional DRAMs allow only one word line to be activated at one time. Because of this limitation, the disturb test described above needs to repeat activation and deactivation with respect to each word line by successively selecting each word line.
Development of integrated-circuit technology makes it possible to manufacture DRAMs of a larger memory capacity, and such DRAMs have a larger number of word lines. As DRAMs have a larger capacity, therefore a time length required for testing a DRAM becomes undesirably lengthy. This raises an expectation for technology which can reduce the test time.
The test time can be reduced if a plurality of word lines can be simultaneously activated during a test mode. Such simultaneous activation can be readily achieved in the following manner.
A row-address decoder is provided inside a DRAM, and decodes a supplied row address to select one word line. Generally, such a row-address decoder receives complement signals as row address signals. That is, if a row address is represented by a set of three bits (A
1
, A
2
, A
3
), the row-address decoder receives signals representing A
1
, A
2
, and A
3
as well as /A
1
, /A
2
, and /A
3
. NAND circuits are provided inside the row-address decoder for the decoding purposes, and each of the NAND circuits receives a corresponding selection of three bits chosen from A
1
, A
2
, A
3
, /A
1
, /A
2
, and /A
3
. For example, a given NAND circuit receives /A
1
, A
2
, and /A
3
. This NAND circuit outputs a LOW signal only when (A
1
, A
2
, A
3
) is (0, 1, 0). In this manner, each NAND circuit generates an output signal representing a corresponding row address.
When a row-address decoder with complement signals is used, it is relatively easy to activate a plurality of word lines simultaneously. This is achieved by forcing both A
3
and /A
3
to be HIGH, for example. In this case, two word lines corresponding to row address (1, 1, 0) and (1, 1, 1) are activated at one time. By the same token, forcing A
2
, /A
2
, A
3
, and /A
3
to be HIGH results in activation of four word lines.
In this manner, a. plurality of word lines can be simultaneously selected if complement signals are supplied to a row-address decoder.
A demand for chip-size reduction, however, requires some DRAM chips to be provided with a row-address decoder receiving only positive-logic signals. Namely, only A
1
, A
2
, and A
3
are supplied without their complements /A
1
, /A
2
, and /A
3
. In such DRAMs, there is no straightforward method to activate a plurality of word lines at the same time.
As demand for a chip-size reduction becomes stronger, more DRAMs will be provided with a row-address decoder receiving only positive-logic signals. Against this background, we need to seek ways to achieve a simultaneous activation of a plurality of word lines for the purpose of reducing the test time.
Accordingly, there is a need for a semiconductor memory device which can reduce a test time of memory cells.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a semiconductor memory device which can achieve the need described above.
It is another and more specific object of the present invention to provide a semiconductor memory device which can reduce a test time of memory cells.
In order to achieve the above objects according to the present invention, a semiconductor memory device capable of conducting test operations includes a plurality of word drivers which keep word lines in an active state when the word drivers are selected until the word drivers are reset, and a control circuit which successively selects more than one of the plurality of word drivers so as to achieve simultaneous activation of word lines corresponding to selected ones of the plurality of word drivers during the test operations.
In the semiconductor memory device described in the above, the plurality of word drivers, when selected, keep word lines in the active state until they are reset, so that successive selection of word drivers can achieve the multiple selection and activation of word lines. Because of this, a time length required for a memory-cell test can be significantly reduced, compared to when only one word line can be activated at one time.
According to one aspect of the present invention, each of the plurality of word drivers includes a latch which can be reset. This latch latches a state which indicates the selection of a corresponding word driver, thereby keeping the active state of the word line.
According to another aspect of the present invention, a signal indicating a row address selects one of the plurality of word drivers, and the state indicative of the selection is latched by a timing pulse.
According to another aspect of the present invention, the multiple-word-line selection is permitted during test operations, but cannot be made during normal operations, which is controlled by a word-line-multiple-selection avoiding circuit. Because of this configuration, only one word line can be activated during the normal operations, while multiple selection of word lines can be achieved during the test operations.
According to another aspect of the present invention, more than one word liens in an active state can be simultaneously deactivated by inputting a precharge command.
According to another aspect of the present invention, redundant-word drivers are operated even during the test operations, so that memory-cell tests can be conducted with respect to redundant memory cells.
According to another aspect of the present invention, a plurality of word lines are successively activated in a multiple manner which enables the plurality of word lines to be simultaneously kept in an active state by drawing on a word-line-multiple-selection function of a semiconductor device. This is done in order to check whether an activated word line has any effect on memory cells of surrounding word lines. Because of the multiple activation of word lines, a time length required for defective-cell tests can be significantly reduced.
According to another aspect of the present invention, data is written in the memory cells of surrounding word lines around word lines, before these word lines are activated in the multiple manner. Then, data is read from the memory cells to check whether data has been changed by the activation of the word lines.
According to another aspect of the present invention, even when there is a limit to a time duration during which the word lines are kept activated, an activation and deactivation of the word lines can be repeated many times, thereby accumulating total time period of word-line activation.
According to another aspect of the present invention, the activation and deactivation of the word lines are repeated for a time duration equivalent to a refresh cycle of memory cells. If no cell defects are dete

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