Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-09-09
2004-06-01
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S230060, C365S189011
Reexamination Certificate
active
06744678
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of masking an undesired column access signal.
DESCRIPTION OF THE PRIOR ART
FIG. 1A
is a schematic circuit diagram showing a path to write data into a memory cell
150
and
FIG. 1B
is a timing chart for the circuit diagram of a prior art shown in FIG.
1
A.
Conventionally, when a data masking signal reaches an active level, global input/output data lines GIO/GIOZ, which are inputted into a write driver
110
, are masked. Namely, data, which are in global input/output data lines GIO/GIOZ, are not transmitted into local input/output data lines so that the data are not written in the memory cell
150
. However, a column access signal Yi, which is a control signal selecting column lines, is not masked.
The column access signal Yi increases the voltage level of the bit line bar BLZ by transmitting the voltage of sub input/output lines SIO/SIOZ charged to an internal voltage level of Vintc bit lines BL/BLZ (NOT SHOWN). When the column access signal Yi disappears, the increased voltage level of the bit line bar BLZ returns to the original voltage level by the operation of a bit line sense amplifier
140
. However, if a precharge command is applied before the increased voltage level of the bit line bar BLZ returns to the original voltage level, the third NMOS transistor NM
3
is turned off because the voltage level of the word line WL becomes a low voltage level in the memory cell
150
. At this time, since the capacitor in the memory cell
150
is still charged with the increased voltage level, an original data, ‘0’, representing the discharged state of the capacitor, is lost. The bank write enable signal bwen inputted into the write driver
110
is a flag signal to enable the write of a bank. A block selection signal bs is a gate control signal to control the first NMOS transistor NM
1
in the block selection unit
120
.
A write signal and data are inputted into the write driver
110
through the global I/O lines with a bank write enable signal bwen. Then the data inputted through the global input/output data lines GI
0
/GI
0
Z are transmitted to local input/output data lines LI
0
/LI
0
Z. When the block selection signal bs is applied to the block selection unit
120
, data is transmitted to the sub input/output lines SIO/SIOZ. When the column access signal Yi is applied to the column selection unit
130
, data is transmitted through the bitline sense amplifier
140
and to the memory cell
150
selected by a wordline and a bitline. If the data is masked at this time, data is not written in the memory cell
150
.
When the write data masking signal wdm is inputted into the write driver
110
to mask the data, in the global input/output lines GIO/GIOZ, data is not transmitted to the local input/output lines LIO/LIOZ. However, a dummy column access signal is generated because control signals, except data, are not masked. When the undesired column access signal is applied to a second NMOS transistor NM
2
in the column selection unit
130
, voltage of the sub input/output lines SIO/SIOZ, which is precharged to Vintc, is applied to the bitline bar blz so that the voltage level of the bitline bar blz increases. If a precharge command is applied and the word line transistor NM
3
is turned off before the voltage level of the bitline bar blz returns to the original voltage level, the increased voltage is written in the memory cell
150
so that the data stored in the memory cell
150
is lost. Therefore, normal operation of the semiconductor memory device cannot be expected.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of masking a dummy column access signal by using a write data masking signal.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device, comprising: a masking means for masking the generation of a column access signal by using a write data masking signal, wherein the masking means includes: a control signal generating means for receiving control signals including a write data masking signal, a column address signal and a read/write strobe signal and outputting a control signal to prevent the enabling of an undesired column access signal and a column address decoding means for outputting a column access signal in response to the control signal from the control signal generating means.
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patent: 5612922 (1997-03-01), McLaury
patent: 5787046 (1998-07-01), Furuyama et al.
patent: 5867447 (1999-02-01), Koshikawa
patent: 5940328 (1999-08-01), Iwamoto et al.
patent: 6151272 (2000-11-01), La et al.
patent: 6175534 (2001-01-01), Taniguchi et al.
patent: 6208582 (2001-03-01), Kanda et al.
patent: 07-220477 (1995-08-01), None
patent: 09-320258 (1997-12-01), None
patent: 10-241362 (1998-09-01), None
patent: 2000-132964 (2000-05-01), None
patent: 1999-85199 (1999-12-01), None
patent: 2001-10042 (2001-02-01), None
Auduong Gene
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
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