Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-07-13
2001-11-06
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230030, C365S230060
Reexamination Certificate
active
06314035
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to their configurations rapidly running a test for improving their reliability.
2. Description of the Background Art
As semiconductor memory devices such as dynamic random access memories (DRAMs) are being increased in memory capacity, the time required for testing such devices is also increased significantly.
This is because as a semiconductor memory device is increased in memory capacity it is also increased in the number of word lines and it thus disadvantageously takes a lot longer time to write and read information to and from memory cells as such word lines are successively placed in a selected state.
This problem becomes severe in an acceleration test such as a burn-in test, which is a total inspection. In the burn-in test, semiconductor memory devices are operated at a high temperature and on a high voltage to manifest various latent initial detects, such as a defective gate insulating film of a constituent MOS transistor, a defective interlayer insulating film between interconnections, a defective interconnection, or a defect attributed to a particle introduced during the device manufacturing process, to eliminate any defective products before the devices are shipped.
Generally, a semiconductor memory device can have a failure mainly in the following three periods: initial failure period, accidental failure period, and wear-out failure period, as arranged in chronological order.
The initial failure period is a period in which a semiconductor device presents as a failure a defect introduced into the device when the device is being manufactured, and it is thus a period in which a failure occurs initially, soon after a semiconductor device is brought into use. The initial failure rate rapidly decreases with time. Thereafter, a low failure rate continues for a long period of time in the accidental failure period. The device then approaches the end of its longevity and thus enters the wear-out failure period, in which its failure rate rapidly increases.
Desirably, a semiconductor device should be used in the accidental failure period. To provide more reliable semiconductor memory devices, any devices which will have an initial failure should be eliminated previously. To do so, semiconductor memory devices are accelerated in operation for a predetermined period of time and thus aged and thus screened to remove any defective products. To screen the devices effectively in a short period of time, it is desirable that a test be conducted allowing a device to have an initial failure rate rapidly decreasing with time and thus enter the accidental failure period as soon as possible.
Currently, semiconductor memory devices can be subjected to a high-temperature operation test such as described above, or a burn-in test, when they are screened. The test is conducted on an actual device to directly estimate the reliability of the gate oxide film of the MOS transistor, operating the device in a high electric field and at a high temperature and thus applying a stress thereto to manifest various defective factors including migration of aluminum interconnection.
As such, such burn-in test as described above is essential in shipping products of high quality and if the test requires longer time then it will directly increase the cost for manufacturing semiconductor memory devices.
A conventional burn-in test is conducted on semiconductor memory devices for example mold-packaged and thus completely assembled. If in such burn-in test any semiconductor memory device is found to have an initial failure then such device may be not shipped as a final product. This means that the chip has been assembled in vain.
To save such a wasteful fabrication cost, a burn-in test (a WBI test hereinafter) can be conducted on a semiconductor memory device in the form of a wafer.
In conducting such WBI test on a semiconductor memory device, its circuit configuration is subjected to a high-temperature acceleration test in two burn-in modes of operation, i.e., a memory-cell burn-in mode and a peripheral-circuitry burn-in mode.
When there are such two modes, in a decode signal unit an interconnection receives a stress in the peripheral circuitry burn-in mode.
In the peripheral circuitry burn-in mode of operation, oftentimes with a DRAM in a self-refresh operation the peripheral circuitry is burn-in operated for example with an external power supply voltage applied as a power supply potential. More specifically, in burn-in testing a semiconductor memory device in the form of a wafer, when the device in a standby state externally receives a potential of a power supply voltage Vcc level externally via a pad exclusively used for a wafer burn-in test (a WBI pad), in the DRAM a test mode detection circuit detects that a wafer burn-in test mode has been set and responsively a stress is applied between word lines.
In such an operation as described above, in a row-related circuit on a path for transmitting a decoded signal there will be a stress applied thereto, although low in duty ratio.
In a column-related circuit, however, a decoded signal is not activated in the self refresh operation, with a disadvantageous result that any stress cannot be applied to a column-related path for transmitting decoded signals, such as a column select line (a CSL line hereinafter).
As a result, if a chip in the form of a wafer is subjected to a burn-in test and determined as being free of any defects it might be a defective product if it is subjected to a burn-in test after it has been assembled and thus complete. Such is not preferable in conducting a burn-in test on a wafer to ensure the reliability of each chip.
SUMMARY OF THE INVENTION
The present invention contemplates a semiconductor memory device capable of applying a stress voltage to a column select line and capable of manifesting a short-circuit failure associated with the column select line.
Briefly speaking, the present invention is a semiconductor device including a memory cell array, a row selected circuit, a plurality of column select lines, a column select circuit, a data input/output circuit, and a stress application circuit.
The memory cell array includes a plurality of memory cells arranged in rows and columns. The row select circuit is responsive to a row address signal for selecting a row of the memory cell array.
The plurality of column select lines selects a column of the memory cell array. The column select circuit is responsive to a column address signal for generating a signal for selectively activating at least one of the plurality of column select lines.
The data input/output circuit transmits and receives data to and from a memory cell column corresponding to an activated one of the plurality of column select lines.
The stress application circuit selectively applies a stress potential to a predetermined one of the plurality of column select lines in a test mode.
Thus a main advantage of the present invention is that in a test period a stress potential can be selectively applied to a predetermined one of a plurality of column select lines to manifest an initial failure and thus screen any defective chips having such failure.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5424990 (1995-06-01), Ohsawa
patent: 6094388 (2000-07-01), Cowles
patent: 5-291368 (1993-11-01), None
Hoshita Tetsushi
Kitade Osamu
Hoang Huan
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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