Semiconductor memory device capable of keeping sensing...

Details Semiconductor memory device capable of keeping sensing... Semiconductor memory device capable of keeping sensing...

2000-10-26

2001-08-21

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S208000

Reexamination Certificate

active

06278650

ABSTRACT:

BACKGROUND OF THE INVENTION
A known architecture for a dynamic random access memory (DRAM) includes multiple memory blocks, where each memory block includes a set of bit line sense amplifiers. When a block is selected for a read operation, the bit line sense amplifiers in the block generate data signals by reading from one or more memory cells in the block. The sense amplifiers then output the data signals to data lines that are connected to data line sense amplifiers. More particularly, each sense amplifier conventionally outputs a pair of signals to a corresponding pair of data lines that are connected to a corresponding data line sense amplifier. The data line sense amplifiers typically include a current sense amplifying unit that senses a difference in currents on the pair of data lines. The sensed data on the data lines can be output from the data line sense amplifier and from the DRAM via data output buffers and multiplexing circuitry.
One problem with using current sensing on the data lines is that the transmission distances from the memory blocks to the data line sense amplifier vary. Accordingly, current from a memory block close to the data line sense amplifier travels a shorter length of the data lines and experiences less resistance on the data lines between the memory block and the data lines sense amplifier. Current from a memory block far away from the data line sense amplifier experiences more resistance on the data lines between that memory block and the data lines sense amplifier. Accordingly, the data line sense amplifier often has different sensing efficiency for different memory blocks. This can lead to differences in access times for read operations, which is particularly undesirable for a memory device such as a synchronous DRAM (SDRAM) where timing of data signals is critical. The problem becomes more significant for larger capacity memories because the relative differences in transmission lengths typically increase with an increase in the memory capacity and the integration density. Accordingly, a semiconductor memory device capable of keeping the sensing efficiency of a data line sense amplifier uniform is required.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a semiconductor memory device keeps the sensing efficiency of a data line sense amplifier uniform. One embodiment of the invention is a semiconductor memory device having pairs of data lines that are shared by a plurality of memory blocks, each having a plurality of memory cells. The device includes load transistors that apply current to the pairs of data lines to which a bit line sense amplifier in the memory blocks transfers memory cell data, during reading. Data line sense amplifiers sense the current differences of the pairs of data lines. To maintain uniform sensing efficiency, the sizes of load transistors far away from the data line sense amplifiers are different from the sizes of load transistors close to the data line sense amplifiers. Preferably, the load transistors far away from the data line sense amplifiers are smaller than load transistors close to the data line sense amplifiers.
Additionally, the semiconductor memory device further includes switching transistors between the bit line sense amplifiers and the pairs of data lines. The switching transistors far away from the data line sense amplifiers can be larger than switching transistors close to the data line sense amplifiers. The switching transistors of different sizes can be use with or without load transistors that have different sizes.
According to an aspect of the present invention, the sensing efficiency of the data line sense amplifier can be kept uniform by differentiating the sizes of load transistors and/or switching transistors of the memory blocks according to the positions of the memory blocks.


REFERENCES:
patent: 4479202 (1984-10-01), Uchida

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