Semiconductor memory device capable of independent selection...

Details Semiconductor memory device capable of independent selection... Semiconductor memory device capable of independent selection...

2001-01-17

2002-02-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230080, C365S225700

Reexamination Certificate

active

06349064

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a configuration of a semiconductor memory device having a redundancy function.
2. Description of the Background Art
A conventional semiconductor memory device is generally pre-provided with a redundant portion in a memory cell array in order to compensate yield reduction due to occurrence of a defection in a memory cell included in the memory cell array.
FIG. 11
schematically illustrates a configuration of such a conventional memory cell array.
Referring to
FIG. 11
, memory cell array
100
includes a normal memory cell array portion
100
n
and a redundant memory cell array portion
100
R.
Redundant memory cell array portion
100
R includes a redundant memory cell row portion
100
RR, a redundant memory cell column portion
100
RC, and a redundant part of the redundant portions
100
RRC.
The memory cell space of normal memory cell array portion
100
n
is tested during a manufacturing process of the semiconductor memory device to detect a defective memory cell. The detected defective memory cell is replaced by a memory cell in redundant memory cell array portion
100
R.
A method for performing such replacement generally includes programming of a defective address corresponding to the defective memory cell using a fuse circuit. The programming of such a defective address is performed by blowing off a fuse using electricity, laser or the like.
Further, a defective memory cell may exist in the memory space for redundant memory cell array portion
100
R. Therefore, the test for the memory cell space during the manufacturing process, as described above, also needs to perform a test for redundant memory cell array portion
100
R.
FIG. 12
is a schematic block diagram for illustrating the configuration of memory cell array
100
shown in
FIG. 11
in more detail.
Referring to
FIG. 12
, normal memory cell array portion
100
n
is provided with word lines WL
0
to WL
15
corresponding to the memory cell rows thereof, whereas redundant memory cell row portion
1
O
0
RR is provided with spare word lines SWL
0
to SWL
3
corresponding to the memory cell rows thereof. Word lines WL
0
to WL
15
are selectively activated by a row decoder
110
decoding a row address signal.
A spare row decoder
112
′ provided corresponding to spare word lines SWL
0
to SWL
3
performs non-volatile storage of a defective row address which includes a defective memory cell by a fuse element or the like, and when the defective row address is accessed, activates one of spare word lines SWL
0
to SWL
3
, for example, spare word line SWL
2
, instead of a word line WLn corresponding to the defective row address.
Further, bit line pairs BL
0
and /BL
0
to BL
15
and /BL
15
are provided in common to normal memory cell array portion
100
n
and redundant memory cell row portion
100
RR, corresponding to the memory cell rows thereof. Spare bit line pairs SBL
0
and /SBL
0
to SBL
3
and /SBL
3
are provided in redundant memory cell column portion
100
RC, corresponding to the memory cell columns thereof. A memory cell MC is provided corresponding to each crossing point of bit line pairs BL
0
, /BL
0
to BL
15
, /BL
15
and spare bit lines SBL
0
, /SBL
0
to SBL
3
, /SBL
3
, and word lines WL
0
to WL
15
and spare word lines SWL
0
to SWL
3
.
Column decoder
120
decodes a column address signal, and selectively activates a sense amplifier and I/O circuit (hereinafter referred to as SA+I/O circuit)
140
for a selected memory cell column, to selectively transmit data read onto a bit line pair corresponding to the selected memory cell column to IO line pairs IO and /IO.
It is noted, in
FIG. 12
, that SA+I/O circuit
140
includes a differential amplifier for amplifying a potential difference of a bit line pair and a gate circuit for selectively connecting the selected bit line pair and IO line pair IO, /IO.
Spare column decoder
122
′ stores a defective column address including a defective memory cell, by a fuse element or the like, and when the defective column address is accessed, selectively connects one of the spare bit line pairs, for example, spare bit line pair SBL
0
and /SBL
0
, to IO line pair IO and /IO, instead of a bit line pair corresponding to the defective column address, for example, a bit line pair BL
12
and /BL
12
.
A testing operation for detecting a defective memory cell for the semiconductor memory device having memory cell array
100
as shown in
FIG. 12
will now be described.
The test for the memory cell space constituted by the conventional memory cell array
100
as shown in
FIG. 12
includes a plurality of types of tests as described below.
(1) The test before a replacement process by a redundant portion includes the following:
(1-1) A test for normal memory cell array portion
100
n
in the memory cell space;
(1-2) A test for redundant memory cell array portion
100
R in the memory cell space.
(2) The test after the replacement process by the redundant portion includes the following:
(2-1) A test for a normal portion (including an address replaced by the redundant portion) in the memory cell space.
Referring to
FIG. 12
, the test for the normal memory cell array portion in the memory cell space described above performed before the replacement process by the redundant portion (1-1) includes a test for the memory cell space corresponding to word lines WL
0
to WL
15
and bit line pairs BL
0
, /BL to BL
15
, /BL
15
.
The test for the redundant memory cell array portion in the memory cell space performed before the replacement process by the redundant portion (1-2) includes tests for three portions as described below.
i) A test for the memory cell space constituted by spare word lines SWL
0
to SWL
3
and bit line pairs BL
0
, /BL
0
to BL
15
, /BL
15
;
ii) A test for the memory cell space constituted by word lines WL
0
to WL
15
and spare bit line pairs SBL
0
, /SBL
0
to SBL
3
, /SBL
3
; and
iii) A test for the memory, cell space constituted by spare word lines SWL
0
to SWL
3
, and spare bit line pairs SBL
0
, /SBL
0
to SBL
3
, /SBL
3
.
If redundant memory cell array portions
100
RR and
100
RC include a defective bit as a result of such tests for the redundancy memory cell array portions, a repair is performed by replacing the defective portion with redundant part of the redundant portions
100
RRC. In such a case, it is unnecessary to completely repair redundant portions
100
RR and
100
RC, and it would be sufficient if there are replaceable spare rows or columns of at least a number required for repairing the defective bit of the normal memory cell array portion.
Further, in the test performed after the replacement process by the redundant memory cell array portion (2-1) when, for example, word line WLn is replaced by a spare word line SWL
2
, a test for the memory cell space constitute by word lines W
10
to WLn−1, SWL
2
, WLn+1 to WL
15
, and bit line pairs BL
0
, /BL
0
to BL
15
,/BL
15
will be performed.
In the memory cell space, the boundaries of the normal memory cell array portion and the redundant memory cell array portion are physically adjacent to each other. Thus, the configurations thereof are basically the same, except for what is used for driving the portions, row decoder
110
and column decoder
120
or redundant row decoder
112
′ and redundant column decoder
122
′.
In other words, they are different in the respect that an address provided upon access of the memory cell array is allocated to normal memory cell array portion
100
n
, whereas no address is allocated to redundant memory cell array portion
100
R since this portion is for replacing a memory cell row or a memory cell column in normal memory cell array portion
100
n.
If, for example, word line WLn is replaced with spare word line SWL
2
as described above, a defective memory cell existing in a memory cell row corresponding to word line WLn will be repaired.
However, malfunction of a defective memory cell MCf
1
corresponding to word line WLn is sometimes caused by

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