Semiconductor memory device capable of imposing large stress...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S189090, C365S230060

Reexamination Certificate

active

06631092

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device capable of placing large stress on a specific transistor in a burn-in test mode.
2. Description of the Background Art
FIG. 19
is a circuit diagram showing configurations of a word line driver and its peripheral in a conventional dynamic random access memory (DRAM). Referring to
FIG. 19
, the word line driver
1
for driving a word line WL includes a P channel MOS transistor
2
and N channel MOS transistors
3
and
4
. A memory cell
5
is connected to word line WL and a bit line BL.
When word line WL is selected, as shown in
FIG. 20A
, a sub-decode signal &phgr; attains an H (logical high) level (of a boosted potential Vpp greater than a power supply potential), a sub-decode signal Z&phgr; attains an L (logical low) level (of a ground potential), and the potential of a main word line ZMWL (i.e., a main word line select signal) attains an L level. As a result, transistor
2
turns on and transistors
3
and
4
turn off, so that the potential of word line WL becomes boosted potential Vpp. Throughout the specification and drawings, a reference character “Z” prefixed to any signal indicates that the relevant signal is low active.
When word line WL is not selected, as shown in
FIG. 20B
, although sub-decode signal &phgr; attains an H level and sub-decode signal Z&phgr; attains an L level, the potential of main word line ZMWL (main word line select signal) is maintained at the H level (of boosted potential Vpp greater than the power supply potential). As a result, transistors
3
and
4
turn on, and transistor
2
basically turns off, while a small leakage current Ilk flows in transistor
2
. If this leakage current Ilk is large, the potential of word line WL will become greater than the ground potential, which is likely to damage data of memory cell
5
. Any DRAM having P channel MOS transistor
2
with such a large leakage current Ilk should be eliminated from end products.
FIG. 21
is a circuit diagram showing configurations of a sense amplifier and its peripheral in a conventional DRAM. Referring to
FIG. 21
, the sense amplifier
6
is connected to a bit line pair BL, ZBL through a bit line isolating gate
7
. Sense amplifier
6
is also connected to an input/output line pair I/O, ZI/O through a column select gate
8
. Column select gate
8
is formed of N channel MOS transistors
81
and
82
. Connected to input/output line pair I/O, ZI/O is a write driver
9
that responds to a write driver enable signal ZWDE and transmits write data WD to bit line pair BL, ZBL. An equalizing circuit
10
is also connected to input/output line pair I/O, ZI/O, which responds to an equalizing signal IOEQ and equalizes the potentials of input/output lines I/O and ZI/O.
When data is being written, as shown in
FIG. 22
, a bit line isolating signal BLI attains an H level, a bit line isolating gate
7
is turned on, and bit line pair BL, ZBL is connected to sense amplifier
6
. Thereafter, when sense amplifier
6
is activated, data of an L level is read out in this example, so that bit line pair BL attains a potential of an L level, and bit line ZBL attains a potential of an H level. Thereafter, when write driver enable signal ZWDE attains an L level, write driver
9
responds to write data WD of an H level in this example, and drives the potential of input/output line I/O to an H level and the potential of input/output line ZI/O to an L level. Thereafter, when a column select signal CSL attains an H level, column select gate
8
is turned on, and the potentials of input/output line pair I/O, ZI/O are transmitted to bit line pair BL, ZBL. In this case, although the potentials of bit line pair BL, ZBL are opposite to the potentials of input/output line pair I/O, ZI/O, write driver
9
is able to reverse the potentials of bit line pair BL, ZBL, since it has driving capability greater than that of sense amplifier
6
. Specifically, the potential of bit line BL is turned to an H level, and the potential of bit line ZBL is turned to an L level.
If transistors
81
and
82
of column select gate
8
each have a large ON resistance, however, the potentials of input/output line pair I/O, ZI/O will not be transmitted sufficiently to bit line pair BL, ZBL while column select signal CSL is at an H Level. In this case, write driver
9
will fail to reverse the potentials of bit line pair BL, ZBL, causing an error in data writing. Therefore, any DRAM having transistors
81
,
82
with such large ON resistances should be eliminated from end products.
A conceivable way of finding the former defective transistor
2
will be, in a burn-in test, to raise the potential of sub-decode signal &phgr; greater than boosted potential Vpp and repeat selection
on-selection of word line WL to accelerate the stress being imposed on transistor
2
, thereby increasing leakage current Ilk. In this case, however, an enormous amount of consumption current will flow. Thus, due to the constraint of the burn-in tester, the frequency of repetition of the selection
on-selection of the word line is limited to some extent.
A possible way to find the latter defective transistors
81
,
82
will be, in a burn-in test, to repeat writing of data of an H level and data of an L level to accelerate the stress being imposed on transistors
81
,
82
, thereby increasing the ON resistances thereof. However, a huge amount of consumption current will flow again in this case. Thus, due to the constraint of the burn-in tester, the data writing cannot be repeated so frequently.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device capable of imposing large stress on a specific transistor.
According to an aspect of the present invention, the semiconductor memory device includes a word line, a word line driver, and a word line select circuit. The word line driver drives the word line. The word line select circuit generates a word line select signal for selecting the word line. The word line driver includes a first transistor and a second transistor. The first transistor has one conductive electrode receiving a boosted potential greater than a power supply potential, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The second transistor has one conductive electrode grounded, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The semiconductor memory device further includes a turn-on circuit which causes the first transistor to turn on in response to a test signal.
In this semiconductor memory device, the first transistor is turned on in response to the test signal even when the word line is non-selected, and a leakage current flows in the first transistor. As a result, it is possible to impose large stress on the first transistor.
According to another aspect of the present invention, the semiconductor memory device includes a plurality of blocks, each of which is selected in response to a corresponding block select signal. Each block includes a word line, a word line driver, and a word line select circuit. The word line driver drives the word line. The word line select circuit generates a word line select signal for selecting the word line. The word line driver includes a first transistor and a second transistor. The first transistor has one conductive electrode receiving a boosted potential greater than a power supply potential, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The second transistor has one conductive electrode grounded, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The semiconductor memory device further includes a turn-on circuit. The turn-on circuit causes the first transistor in selected one of the blocks to turn on in response

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