Semiconductor memory device capable of holding write data...

Details Semiconductor memory device capable of holding write data... Semiconductor memory device capable of holding write data...

2003-03-05

2004-06-01

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S145000

Reexamination Certificate

active

06744658

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device, which has a long refresh cycle, and can accurately amplify data read from a memory cell.
2. Description of the Background Art
For providing an on-chip large-scale memory in a system LSI (Large Scale Integration), it is necessary to fabricate a memory portion by a CMOS (Complementary MOS) logic process for suppressing increase in cost and preventing lowering of a performance of a logic circuit.
An SRAM (Static Random Access Memory) is a kind of memory, which can be fabricated by the CMOS logic process. However, various problems arise if the capacity of the SRAM is increased.
First, if the SRAM employs memory cells formed of the CMOS, one memory cell requires six transistors, and therefore occupies a large area. Therefore, increase in capacity results in increase in area of the whole system chip, and therefore results in increase in cost and lowering of yield.
As a result of miniaturization in the CMOS process, a non-negligible off-leakage current occurs in the transistors of the memory cell, and standby current unavoidably increases.
In view of the above problems, a planar DRAM (Dynamic Random Access Memory), which can be fabricated by the CMOS logic process, may be used. The planar DRAM has a smaller area than the SRAM, and periodically requires a smaller refresh current so that the standby current can be smaller than that of the SRAM, and thus the planar DRAM is very useful.
Referring to
FIG. 17
, a memory cell
200
in a planar DRAM is formed of P-channel MOS transistors
201
and
202
. P-channel MOS transistor
201
is connected between a bit line BLi (i: natural number satisfying (0≦i≦m), where m is a natural number) and a node NS. P-channel MOS transistor
201
has a gate terminal connected to a word line WLj (j: natural number satisfying (0≦j≦n), where n is a natural number).
P-channel MOS transistor
202
has source and drain terminals connected to a node NS, and receives on its gate terminal a cell plate voltage VCP formed of a ground voltage GND.
Word line WLj carries a power supply voltage Vcc during standby, and carries ground voltage GND when it is active.
When word line WLj is active, P-channel MOS transistor
201
is on so that data is sent to or from a channel region (i.e., node NS) of P-channel MOS transistor
202
via P-channel MOS transistor
201
.
FIG. 18
shows a layout of memory cells of a planar DRAM. Referring to
FIG. 18
, active regions
203
and
204
are formed on a deeper side of a sheet of
FIG. 18. A
cell plate
205
and word lines WLj−1 and WLj are formed on active region
203
. A cell plate
206
is formed over both active regions
203
and
204
, and a cell plate
207
and word lines WLj+1 and WLj+2 are formed on active region
204
. A bit line pair BLi and /BLi is formed in a direction perpendicular to word lines WLj−1-WLj+2. A contact
208
is formed between word lines WLj−1 and WLj for connecting bit line BLi to a source terminal of a transistor formed under word line WLj. Also, a contact
209
is formed between word lines WLj+1 and WLj+2 for connecting bit line /BLi to a source terminal of a transistor formed under word line WLj+1.
FIG. 19
is a cross section of a region
210
shown in FIG.
18
. Referring to
FIG. 19
, an N-well
221
is formed at a surface layer of a p-type silicon substrate
220
. P
+
diffusion layers
222
and
223
are formed at portions of N-well
221
. A gate
224
is formed on N-well
221
located between P
+
diffusion layers
222
and
223
. Word line WLj is formed on gate
224
.
A gate
225
is formed on N-well
221
neighboring to P
+
diffusion layer
223
, and a cell plate
204
is formed on gate
225
. Contact
208
is formed on P
+
diffusion layer
222
, and connects bit line BLi to P
+
diffusion layer
222
. Insulating portion
208
A is formed at N-well
221
of the region neighboring to gate
225
. Insulating portion
208
A is used for element isolation.
P
+
diffusion layers
222
and
223
as well as gate
224
form P-channel MOS transistor
201
, and P
+
diffusion layers
223
and gate
225
form P-channel MOS transistor
202
.
Cell plate
204
is supplied with cell plate voltage VCP formed of ground voltage GND. Therefore, an inverted layer
226
is formed at the surface of N-well
221
under cell plate
204
when positive charges are accumulated as a result of writing of H-data.
Referring to
FIG. 20
, an operation of writing H-data will now be described. The “H-data” means data written with a high voltage. When the voltage on word line WLj lowers from power supply voltage Vcc to ground voltage GND, word line WLj becomes active so that P-channel MOS transistor
201
is turned on. Positive charges forming the H-data on bit line BLi flow through P
+
diffusion layer
222
and the channel region into P
+
diffusion layer
223
. Since ground voltage GND is placed on cell plate
204
, a sufficient potential difference is present between P
+
diffusion layer
223
and cell plate
204
so that a large amount of positive charges flow from P
+
diffusion layer
223
into the channel region of P-channel MOS transistor
202
. Consequently, inverted layer
226
is formed at the channel region of P-channel MOS transistor
202
. Therefore, the H-data can be easily written into the memory cell of the planar type. When the H-data is written into the memory cell, the memory cell has a large cell capacity.
Referring to
FIG. 21
, an operation of writing L-data will now be described. The “L-data” means data written with a low voltage. When the voltage on word line WLj lowers from power supply voltage Vcc to ground voltage GND, word line WLj becomes active so that P-channel MOS transistor
201
is turned on. Negative charges forming the L-data on bit line BLi flow through contact
208
into P
+
diffusion layer
222
. The negative charges in P
+
diffusion layer
222
do not sufficiently flow into P
+
diffusion layer
223
through the channel region of P-channel MOS transistor
201
due to a threshold loss in P-channel MOS transistor
201
. Since the voltage placed on cell plate
204
is ground voltage GND, a sufficient potential difference does not occur between P
+
diffusion layer
223
and cell plate
204
, and an amount of negative charges flowing from P
+
diffusion layer
223
into the channel region of P-channel MOS transistor
202
is small. Consequently, inverted layer
226
is not formed at the surface of N-well
221
under cell plate
204
. As described above, the cell capacity of the memory cell carrying the L-data is very small.
Description will now be given on an operation of reading data from the memory cell of the planar type. Immediately before the read operation, bit line pair BLi and /BLi is precharged to carry a precharge voltage Vcc/2. When the voltage on word line WLj lowers from power supply voltage Vcc to ground voltage GND, word line WLj becomes active so that P-channel MOS transistor
201
is turned on. The charges held in P-channel MOS transistor
202
flow to bit line BLi through P-channel MOS transistor
201
and contact
208
, and the voltage on bit line BLi slightly changes from precharge voltage Vcc/2 in accordance with the logical level of read data.
More specifically, the voltage on bit line BLi changes from precharge voltage Vcc/2 to a voltage of (Vcc/2+&Dgr;V) when the memory cell has stored H-data. When the memory cell has stored L-data, the voltage on bit line BLi changes from precharge voltage Vcc/2 to a voltage of (Vcc/2−&Dgr;V).
The data read onto bit line BLi is amplified by a sense amplifier SA. Referring to
FIG. 22
, sense amplifier SA includes P-channel MOS transistors
227
-
229
and N-channel MOS transistors
230
-
232
. P-channel MOS transistor
227
is connected between a power supply node NVC and a node N
5
. P-channel MOS transistor
227
receives on its gate a

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