Semiconductor memory device capable of high speed operation in l

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit

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36518909, G11C 700

Patent

active

058417060

ABSTRACT:
A semiconductor memory device includes a memory cell array which is composed of a plurality of memory cells arranged in a matrix manner. Each of rows of the memory cell array is connected to a word line and each of columns of the memory cell array is connected to a pair of bit lines, and one of the word lines and one of the pairs of bit lines are selected in accordance with an address such that one of the plurality of memory cells is selected. An internal signal generating section generates a first activation signal in response to input of the address, and a power supply voltage detecting section determines whether a power supply voltage is higher than a predetermined voltage and generates a voltage detection signal when the power supply voltage is higher than the predetermined voltage. The selected word line is normally set to the power supply voltage and is set to a boosted voltage in response to the voltage detection signal. The boosted voltage is higher than the power supply voltage. A timing control section receives the first activation signal and generates a second activation signal at a timing which is determined based on the voltage detection signal from the power supply voltage detecting section, and a sense amplifier section is responsive to the second activation signal to amplify potentials on the bit lines associated with the selected memory cell and to output the amplifying result as a data stored in the selected memory cell.

REFERENCES:
patent: 5249156 (1993-09-01), Hagiwara et al.
patent: 5384745 (1995-01-01), Konishi et al.

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