Semiconductor memory device capable of fast testing without exte

Details Semiconductor memory device capable of fast testing without exte Semiconductor memory device capable of fast testing without exte

1997-08-04

2000-05-16

Tu, Christine

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

365201, 365226, G11C 2900, G11C 700

Patent

active

060651431

ABSTRACT:
A row address signal output from an internal row address generation circuit according to an output from a ring oscillator activated in response to an externally applied burn-in mode designation signal SBT, is scrambled by an operation circuit and then applied to a row decoder. Meanwhile, a signal output from a data output circuit in response to activation of signal SBT is scrambled by a data scrambler and checker pattern data is applied to a memory cell array such that it corresponds to a physical address of the memory cell array.

REFERENCES:
patent: 5034923 (1991-07-01), Kuo et al.
patent: 5463585 (1995-10-01), Sanada
patent: 5483488 (1996-01-01), Sanada
patent: 5742615 (1998-04-01), Konodo et al.
patent: 5764576 (1998-06-01), Hidaka et al.

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