Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Patent
1991-09-30
1993-12-28
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Accelerating charge or discharge
307451, 36523003, G11C 700
Patent
active
052745970
ABSTRACT:
A divided word line driving circuit applicable to a static random access memory (SRAM) employing a divided word line method is disclosed. When a divided word line is activated, the potential at the input of an inverter for driving the word line is brought to a low level. When the input signals S1 and S2 are both at a low level, the divided word line is brought to an inactive state. The input of the inverter is charged by a transistor 101 in addition to a transistor 102 which is always on. In other words, transistor 101 contributes to accelerating charging of the input of the inverter. Consequently, the potential of the divided word line is made to rise at high speed, so that access operation at high speed can be achieved. The circuit is implemented with a small number of transistors, so that it becomes also possible to enhance the degree of integration of a SRAM.
REFERENCES:
patent: 4516224 (1985-05-01), Aoyama
patent: 4710649 (1987-12-01), Lewis
ISSCC Digest of Technical Papers, by Aizaki et al., entitled "A 15ns 4 Mb CMOS SRAM", Feb. 19, 1990, pp. 126-127.
Ohba Atsushi
Ohbayashi Shigeki
Shiomi Toru
Glembocki Christopher R.
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
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