Semiconductor memory device capable of detecting memory cell...

Details Semiconductor memory device capable of detecting memory cell... Semiconductor memory device capable of detecting memory cell...

2001-11-14

2002-11-05

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S207000

Reexamination Certificate

active

06477096

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, in particularly, to a semiconductor memory device capable of detecting a memory cell having little margin from a plurality of memory cells arranged in a matrix.
2. Description of the Background Art
Attention is being paid to semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory) as memories capable of inputting/outputting data at high speed.
Referring to
FIG. 23
, a conventional DRAM
1000
includes a VccS generating circuit
1010
, a Vbl generating circuit
1020
, a Vcp generating circuit
1030
, a memory cell array
1040
, and a pad
1050
.
VccS generating circuit
1010
drops an external source voltage Vdd supplied from a terminal to thereby generate a memory array voltage VccS, and outputs the generated memory array voltage VccS to memory cell array
1040
. Vbl generating circuit
1020
drops external source voltage Vdd supplied from a terminal to thereby generate a precharge voltage Vbl (=Vdd/2) and outputs the generated precharge voltage Vbl to memory cell array
1040
.
Vcp generating circuit
1030
drops external source voltage Vdd supplied from a terminal to thereby generate a cell plate voltage Vcp, and outputs the generated cell plate voltage Vcp to memory cell array
1040
. Pad
1050
supplies a ground voltage Gnd supplied from a terminal to memory cell array
1040
.
Memory array voltage VccS and ground voltage Gnd are supplied to a sense amplifier (not shown) for determining a logic level of data read from a memory cell and amplifying the read data. The sense amplifier amplifies the read data by increasing a voltage on one of a bit line pair BL and /BL to memory array voltage VccS and decreasing a voltage on the other of bit line pair BL and /BL to ground voltage Gnd in response to the logic level of the read data. Specifically, as shown in
FIG. 24
, before the operation of reading data from memory cells is started, the bit line pair BL and /BL is equalized to precharge voltage Vbl (=Vdd/2) by an equalizing circuit. When reading of data “1” from a memory cell is started at timing T
1
, a very small potential difference occurs between the bit line pair BL and /BL. In this case, a potential on bit line BL becomes Vdd/2+&agr;, and a potential on bit line /BL remains as precharge voltage Vbl (=Vdd/2).
The potentials (Vdd/2+&agr; and Vdd/2) on bit line pair BL and /BL are transmitted to the sense amplifier. On the basis of the potentials (Vdd/2+&agr; and Vdd/2), the sense amplifier determines the logic level of the read data. The sense amplifier starts amplifying operation at timing T
2
to increase the potential on bit line BL to memory array voltage VccS and decrease the potential on bit line /BL to ground voltage Gnd. In this case, during the period from timing T
1
to timing T
2
, ground voltage Gnd supplied to memory cell array
1040
floats. In the case where the data read from a memory cell is “0”, the potential on bit line BL and that on bit line /BL are inverse to each other.
In such a manner, the data read from the memory cell is amplified by the sense amplifier. Memory array voltage VccS and ground voltage Gnd are used for the amplification of the read data by the sense amplifier.
Referring again to
FIG. 23
, precharge voltage Vbl is supplied to the equalizing circuit (not shown) for equalizing the bit line pair BL and /BL. The equalizing circuit equalizes the bit line pair BL and /BL to precharge voltage Vbl (=Vdd/2) before data is read or written. Cell plate voltage Vcp is supplied to one of electrodes (cell plate electrode) of a capacitor for storing data included in a memory cell.
An operation test is conducted on a DRAM before shipment. The operation test is carried out under a condition that a margin of a certain extent is provided to a product standard. For example, when the product standard of source voltage Vdd is 3.3V±0.3, a test is conducted while changing source voltage Vdd in a range from 2.7V to 3.9V or while fluctuating source voltage Vdd from 3.0V to 3.6V in an operative state. A test under combined various timing conditions is also conducted.
Various tests are carried out as described above in order to detect a memory cell having little margin. The “memory cell having little margin” denotes a memory cell which cannot hold data, a memory cell in which a read error occurs, and a memory cell in which a write error occurs. The memory cell having no margin often occurs due to an influence of noise caused in the operation of the DRAM.
In the conventional DRAM, however, since memory array voltage VccS, precharge voltage Vbl, cell plate voltage Vcp, and ground voltage Gnd are supplied from generating circuits and pad for generating the voltages directly to memory cells, a problem such that a number of tests have to be conducted to detect a memory cell having little margin occurs.
SUMMARY OF THE INVENTION
An object of the invention is, therefore, to provide a semiconductor memory device capable of easily detecting a memory cell having little margin.
According to the invention, a semiconductor memory device has: a memory cell array for inputting/outputting data; and a source voltage supplying circuit for supplying an internal source voltage for performing a sensing operation of amplifying read data read from a memory cell included in the memory cell array in response to a logic level of the read data. The memory cell array includes: a plurality of memory cells; a plurality of bit line pairs provided in correspondence with the plurality of memory cells; a plurality of equalizing circuits provided in correspondence with the plurality of bit line pairs, for equalizing the bit line pair to a precharge voltage; and a plurality of sense amplifiers provided in correspondence with the plurality of bit line pairs, for increasing a voltage on one of the bit line pair to a memory array voltage and decreasing a voltage on the other of the bit line pair to a ground voltage in response to the logic level of the read data in the sensing operation. In a normal operation mode, the source voltage supplying circuit supplies the internal source voltage directly to the memory cell array and, in a test mode, the source voltage supplying circuit supplies the internal source voltage to the memory cell array via an impedance.
Preferably, the internal source voltage is a ground voltage, and the source voltage supplying circuit supplies the ground voltage to each of the plurality of sense amplifiers.
Preferably, the semiconductor memory device further includes: a test signal generating circuit for generating a test signal having either a first logic level or a second logic level; and a pad to which the ground voltage is supplied, and the source voltage supplying circuit includes: an output node for supplying the ground voltage to the sense amplifier; and a ground voltage supplying circuit for supplying the ground voltage directly to the output node on receipt of a test signal having the first logic level, and for supplying the ground voltage to the output node via the impedance on receipt of a test signal having the second logic level.
Preferably, the pad includes: a first pad to which the ground voltage is supplied in the normal operation mode; and a second pad to which the ground voltage is supplied in the test mode. The output node is connected to the first pad, the ground voltage supplying circuit includes a plurality of MOS transistors connected in parallel between the output node and the second pad, each of the plurality of MOS transistors is turned off when the test signal having the first logic level is received at its gate terminal and is turned on when the test signal having the second logic level is received at its gate terminal. In the test mode, the test signal generating circuit outputs the test signal having the second logic level to a predetermined number of MOS transistors among the plurality of MOS transistors and outputs the test

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