Semiconductor memory device capable of correctly and surely...

Details Semiconductor memory device capable of correctly and surely... Semiconductor memory device capable of correctly and surely...

2000-08-18

2003-04-22

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S017000, C438S239000, C438S244000, C438S250000, C438S253000, C257S068000, C257S071000, C257S905000, C257S906000, C257S907000, C257S908000, C257S048000, C716S030000

Reexamination Certificate

active

06551846

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a structure for applying voltage stress between memory cells in a dynamic semiconductor memory device. More particularly, the invention relates to a structure for applying voltage stress between adjacent memory cell capacitors using a small number of signals.
2. Description of the Background Art
An acceleration test called burn-in test is performed for removing, from produced devices, any device having a short life time so as to ship the remaining ones. In this acceleration test, the produced devices are operated for a certain period of time under conditions severer than actual conditions in use, and any device having a short life time is broken. In other words, this acceleration test uses stress acceleration to reveal any potential defect which was not detected in a normal failure detection test.
Concerning a dynamic semiconductor memory device (hereinafter referred to as DRAM), the most important test is the burn-in test applied to memory cells accounting for a large percentage of elements on the device. However, with the remarkable increase in the storage capacity of the DRAM, only a small part of the total memory cells operates in one normal operating cycle of the DRAM. The number of memory cells connected to one word line is limited and the number of word lines selected in a normal operation at a time is determined by the refresh cycle. For example, in a 256M DRAM with 8K refresh cycle, only {fraction (1/8192)} (8K) of the total memory cells are selected in one normal operation cycle. In order to perform a burn-in test on all the memory cells, a memory cell row should be selected 8K times, which causes increase of time required for the burn-in test.
“1996 Symposium on VLSI Circuits, Digest of Technical Papers” discloses on pages 194 and 195, for example, a structure in which a greater number of word lines are selected simultaneously and accordingly a greater number of memory cells are selected than in a normal operation, in order to shorten the time required to do the burn-in test.
FIG. 25
is a schematic diagram illustrating a word line drive control unit disclosed in the document above. In
FIG. 25
, the word line drive control unit includes a block decoder
500
receiving test mode row decoder latch instruction signal TM_RDLTC and a row address signal RowAddr, a level shifter
501
boosting H level of an output signal of block decoder
500
to generate a block selection signal BLKSEL, a word line (WL) reset circuit
502
receiving test mode word line latch instruction signal TM_WLLTC, test mode word line reset instruction signal TM_WLRST and an internal row address strobe signal RAS, a level shifter
503
receiving a word line activation instruction signal WLON, a predecode signal X
12
and a word line inactivation instruction signal WLOFF from WL reset circuit
502
to generate a word line activation timing signal and a word line reset timing signal, a buffer circuit
504
buffering the timing signals from level shifter
503
to generate a word line drive signal WLDV, and an NOR circuit
505
receiving the timing signals from level shifter
503
and word line drive signal WLDV from buffer circuit
504
to generate a word line reset signal WLRST.
When test mode row decoder latch instruction signal TM_RDLTC attains the active state, block decoder
500
maintains its set state without being reset regardless of the state of row address signal RowAddr, and fixes block selection signal BLKSEL at H level (when a memory block is selected).
In a normal operation mode, WL reset circuit
502
drives word line reset timing signal WLOFF into the active state according to internal row address strobe signal RAS. In a test mode, WL reset circuit
502
maintains word line reset timing signal WLOFF in the inactive state during the period in which test mode word line latch instruction signal TM_WLLTC is in the active state, and drives word line reset timing signal WLOFF into the active state when test mode word line reset instruction signal TM_WLRST is supplied.
Level shifter
503
receives word line activation timing signal WLON and predecode signal X
12
to generate a word line drive timing signal in the active state according to word line activation timing signal WLON when predecode signal X
12
is in the active state. Level shifter
503
maintains this state until word line reset timing signal WLOFF is activated.
NOR circuit
505
drives word line reset signal WLRST into the active state of H level when word line drive signal WLDV reaches the inactive state and an output signal of level shifter
503
attains L level. During the period in which word line drive signal WLDV is in the active state of H level, NOR circuit
505
maintains word line reset signal WLRST in the inactive state of L level.
The word line drive control unit further includes a decode circuit
506
a
corresponding to a word line WLi+1, being activated in response to activation of block selection signal BLKSEL from level shifter
501
and decoding predecode signals XAij and XAkl, a latch circuit
507
a
inverting and latching an output signal of decode circuit
506
a
, a word line drive circuit
508
a
transmitting word line drive signal WLDV to the associated word line WLi+1 when an output signal of latch circuit
507
a
is in the active state of L level, and a reset transistor
509
a
responsive to activation of word line reset signal WLRST for resetting word line WLi+1 to the ground voltage level.
Similarly, a decode circuit
506
b
activated in response to activation of block selection signal BLKSEL to decode predecode signals XAij and XAkl, a latch circuit
507
b
inverting and latching an output signal of decode circuit
506
b
, a word line drive circuit
508
b
transmitting word line drive signal WLDV to an associated word line WLi when an output signal of latch circuit
507
b
is in the active state of L level, and a reset transistor
509
b
which is turned on when word line reset signal WLRST is activated to reset word line WLi to the ground voltage level are provided corresponding to word line WLi.
Different combinations of predecode signals are respectively provided to decode circuits
506
a
and
506
b
. In a memory block selected by block selection signal BLKSEL, one word line is selected from a group of word lines selected by predecode signal X
12
according to predecode signals XAij and XAkl. An operation in a test mode of the word line drive control unit shown in
FIG. 25
is now described in conjunction with the signal waveform diagram illustrated in FIG.
26
.
In the test mode, test mode instruction signal TM is first activated and simultaneously test mode row decoder latch instruction signal TM_RDLTC and test mode word line latch instruction signal TM_WLLTC are driven into the active state. Accordingly, block decoder
500
is set into a latching state and WL reset circuit
502
is set into a latching state.
In this test mode setting, word line activation timing signal WLON is in the inactive state, word line activation timing signal from level shifter
503
is at L level, word line drive signal WLDV is at L level, word line reset signal WLRST is at H level, and word lines WLi+1 and WLi are maintained at L level. Since no row address is supplied, block selection signal BLKSEL from level shifter
501
is at L level.
In this test mode, externally supplied row address strobe signal /RAS is driven into the active state of L level and simultaneously a row address signal is supplied. According to the row address signal, block decoder
500
is selected, an output signal of block decoder
500
rises to H level, and the H level is latched according to test mode row decoder latch instruction signal TM_RDLTC. Thus, block selection signal BLKSEL from level shifter
501
is fixed at H level in this test mode period. Block selection signal BLKSEL is fixed at H level and decode circuits
506
a
and
506
b
are activated.
According to externally supplied row

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