Semiconductor memory device capable of concurrently...

Details Semiconductor memory device capable of concurrently... Semiconductor memory device capable of concurrently...

2000-12-07

2002-12-31

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S220000, C365S230030, C365S189070, C365S189050, C365S195000, C365S189080, C714S719000, C714S718000

Reexamination Certificate

active

06501690

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory array including a plurality of memory banks, and, more particularly, to a memory diagnostic circuit and a method for diagnosing a plurality of memory banks.
2. Description of the Related Art
In a semiconductor memory device, such as a DRAM or the like, a memory array is divided into a plurality of banks which can independently be operated.
In such a semiconductor memory device, it is necessary to diagnose whether a defect exists in each memory bank, after the complete manufacture of the semiconductor memory device and before shipping of the device. Hence, a circuit for diagnosing the memory is included inside the semiconductor memory device or externally connected thereto.
In conventional memory diagnostic circuits, the diagnosis of any defect in each memory array of the semiconductor memory device is performed in the unit of memory banks. Therefore, in the conventional memory diagnostic circuits, the more the number of banks, the longer the time for diagnosing the memory device.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a memory diagnostic circuit which can complete diagnosing a memory array including a plurality of memory banks in a memory device within a short period of time even if the number of memory banks increases.
In order to accomplish the above object, according to the first aspect of the present invention, there is provided a method for diagnosing a memory array including a plurality of memory banks which can independently read/write data, said method comprising:
parallelly writing identical data into the plurality of memory banks, when diagnosing the memory array;
reading out storage data from the plurality of memory banks; and
comparing the data read out from the plurality of memory banks and the written data, determining that the memory banks are in a normal state when the read data and the written data coincide with each other, and determining that a defect exists in either one of the memory banks when the read data and the written data do not coincide with each other.
According to the above method, the memory including the plurality of banks can be diagnosed at one time. Hence, there is no need to diagnose the memory for each bank. This results in that the diagnosing can be completed within a short period of time, regardless of the number of the banks.
In order to achieve the above object, according to the second aspect of the present invention, there is provided a memory diagnostic circuit for diagnosing a memory array divided into a plurality of memory banks which can independently read/write data, said circuit comprising:
a diagnostic controlling section which writes predetermined common data into the plurality of memory banks, and parallely reads out storage data from the plurality of memory banks;
a memory which stores the predetermined common data written into the plurality of memory banks; and
a comparison circuit which compares the data read out from the plurality of memory banks with the write-data stored in said memory, and outputs a comparison result.
In the memory diagnostic circuit of this invention, when to diagnose the memory array divided into the plurality of memory banks, the diagnostic controller controls the memory banks to collectively write data at one time, and the comparison circuit compares the written data and the data from the memory banks. In this structure, the plurality of memory banks can be diagnosed at one time. Hence, the diagnosing the plurality of memory banks can be achieved within a short period of time, regardless of the number of the memory banks.


REFERENCES:
patent: 6088823 (2000-07-01), Ayres et al.
patent: 6247153 (2001-06-01), Jeon et al.
patent: 6263461 (2001-07-01), Ayres et al.
patent: 60-115099 (1985-06-01), None
patent: 63-201858 (1988-08-01), None
patent: 2-17555 (1990-01-01), None
patent: 4-251355 (1992-09-01), None

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