Semiconductor memory device capable of changing the...

Details Semiconductor memory device capable of changing the... Semiconductor memory device capable of changing the...

2003-06-17

2004-02-24

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S230060, C365S225700, C365S189070

Reexamination Certificate

active

06697292

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-095401, filed on Mar. 31, 2003, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and column selecting and testing methods of the device. More particularly, the invention is concerned with a semiconductor memory device which can sequentially access the m sense amplifiers (m=1, 2, . . . n) among n sense amplifiers (n is a natural number) connected to one data input/output line, in time series, without specifying from the outside of the device.
2. Description of the Related Art
Recently, in a high-speed and highly integrated semiconductor memory device, as the wiring resistance and contact resistance caused by shrinkage increase, the resistance of the elements tends to increase. Conversely, the device operating speed tends to increase as the transistor operating speed increases. Particularly, in DRAM (Dynamic Random Access Memory), there is a problem of an insufficient data writing error caused by the resistance on the route of accessing a memory cell (e.g., refer to “DRAM scaling-down 0.1 &mgr;m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug”, Beom-Jun, Jin et al, Symposium on VLSI Technology. Digest of Technical Papers, pp. 127-128, and “A 6.25 ns random access 0.25 &mgr;m embedded DRAM”, DeMone, P. et al, Simposium on VLSI Circuits Digest of Technical Papers, 2001, pp. 237-240).
Generally, a highly integrated semiconductor memory device employs redundancy technology to replace a defective cell with a redundant cell. Even for the above-mentioned cell with defective-resistance (hereinafter, referred to as a high resistance cell), usually, a replacement method using a spare row or column cell is adopted. However, in addition to a decrease of yield due to the cell's own defect, the yield will also be decreased by replacing a high-resistance cell by a spare cell. Further, in most cases, a high-resistance cell is found only by a high speed test, and is difficult to be found by a test using a low speed tester that is usually used for detection of defects. Moreover, there is a problem that a high resistance cell will become defective even if a test is performed with a high speed tester after packaging.
Further, in order for a semiconductor memory device to cover an increase in the required memory capacity and delay in the latency of memory cells, in recent semiconductor memory devices, it is often demanded to sequentially access a plurality of sense amplifiers connected to the same data input/output line, in time series, without specifying from outside the device.
FIG. 12
shows a configuration of the essential parts of a semiconductor memory device (e.g., DRAM) for which the above-mentioned operation is demanded. In
FIG. 12
, a reference numeral
101
denotes a memory cell. One memory cell
101
stores 1-bit cell data. In this example, each memory cell
101
is connected to one of multiple word lines WL [j] (j=0, . . . , j−1) and one of eight bit lines BL [i] (i=0, . . . ,7). The bit lines BL [
0
] to BL [
7
] are connected to eight sense amplifiers
102
(
102
a
to
102
h
). Reading and writing the cell data for each memory cell
101
are performed through each sense amplifier
102
a
to
102
h.
The reference numerals
103
a
and
103
b
denote a sense amplifier writing/reading circuit. The sense amplifier writing/reading circuit
103
a
is connected to an external data input/output line DIa/DOa (an external data input line DIa/external data output line DOa) and an internal data line DQa. The sense amplifier writing/reading circuit
103
b
is connected to an external data input/output line DIb/DOb (an external data input line DIb/external data output line DOb) and an internal data line DQb. In this example, one internal data line DQa is connected to four sense amplifiers
102
a
to
102
d
through a column selection gate
104
. The other internal data line DQb is connected to four sense amplifiers
102
e
to
102
h
through a column selection gate
104
. Namely, among the eight sense amplifiers
102
a
to
102
h
, the four sense amplifiers
102
a
to
102
d
connected to the bit lines BL [
0
] to BL [
3
] are connected commonly to the same external data input/output lines DIa and DOa. Similarly, the four sense amplifiers
102
e
to
102
h
connected to the bit lines BL [
4
] to BL [
7
] are commonly connected to the same external data input/output lines DIb/DOb.
The column selection gate
104
includes eight NMOS transistors. Among these eight NMOS transistors, the drains of four NMOS transistors are connected to the bit lines BL [
0
] to BL [
3
]. Each source is commonly connected to one internal data line DQa, and the gates are connected to the column selection lines CSL [
0
] to CSL [
3
]. Similarly, the drains of the other four NMOS transistors are connected to the bit lines BL [
4
] to BL [
7
], and each source is commonly connected to the other internal data line DQb, and the gates are connected to the column selection lines CSL [
0
] to CSL [
3
], respectively.
A reference numeral
105
denotes a column selector circuit. The column selector circuit
105
selects one of the column selection lines CSL [
0
] to CSL [
3
] on the time series according to a clock signal CLKC and a control signal.
FIG. 13
shows one memory cell taken out of the above-mentioned DRAM. The above-mentioned bit line BL [i] and the above-mentioned internal data lines DQa/DQb are actually complementary. For example, as shown in
FIG. 13
, the bit line BL [
0
] consists of bit lines BLt [
0
] and BLc [
0
] (or, BLt/c [
0
]). The internal data line DQa consists of internal data lines DQta and DQca (or, DQt/ca).
The memory cell
101
is connected to one of the bit line BLt [
0
] and bit line BLc [
0
]. (In this example, the memory cell
101
is connected to the bit line BLt [
0
].) The memory cell
101
has a cell transistor
101
-1
and a cell capacitor
101
-2
. The cell transistor
101
-1
is an NMOS transistor, whose source is connected to the bit line BLt [
0
] and the gate is connected to the word line WL [j], respectively. The drain of the NMOS transistor is connected to one end of the cell capacitor
101
-2
, and functions as a storage node (SN). The other end of the cell capacitor
101
-2
is connected to a fixed potential (VPL). Writing the cell data is realized by storing electric charges in the cell capacitor
101
-2
. For the electric charge holding characteristic of the cell capacitor
101
-2
, a negative fixed voltage (VBB) is usually applied to the back bias terminal of the cell transistor
101
-1
.
The sense amplifier
102
a
is connected to the bit lines BLt [
0
] and BLc [
0
], respectively. As a sense amplifier
102
a
, for example, a dynamic latch type circuit is used.
The column selection gate
104
includes two NMOS transistors, whose drains are connected to the bit lines BLt [
0
] and BLc [
0
]. Each gate is commonly connected to the column selection line CSL [
0
], and the sources are connected to the internal data lines DQta and DQca, respectively. The internal data lines DQta and DQca are connected to the above-mentioned sense amplifier writing/reading circuit
103
a
, as shown in FIG.
12
.
FIG. 14
shows the operation of the DRAM configured as mentioned above. CLK is an operation clock necessary for operating the DRAM. COM is a command signal supplied from an external device. A read command (R) or a write command (W) is inputted at a certain timing. Here, description will be given on the

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