Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-08-16
2011-08-16
Rizk, Sam (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S752000, C714S758000, C714S769000
Reexamination Certificate
active
08001450
ABSTRACT:
The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
REFERENCES:
patent: 3836957 (1974-09-01), Duke et al.
patent: 4404673 (1983-09-01), Yamanouchi
patent: 6678860 (2004-01-01), Lee
patent: 7739576 (2010-06-01), Radke
patent: 7810017 (2010-10-01), Radke
patent: 2004/0243887 (2004-12-01), Sharma et al.
patent: 2005-044386 (2005-02-01), None
Miyo Toshiya
Onishi Yasuhiro
Arent & Fox LLP
Fujitsu Semiconductor Limited
Rizk Sam
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