Semiconductor memory device capable of automatically...

Details Semiconductor memory device capable of automatically... Semiconductor memory device capable of automatically...

2000-06-16

2002-04-02

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06366492

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a SRAM (a Static Random Access Memory), and more particularly, it relates to bit line loads for bit lines in a SRAM, which is capable of accelerating a recovery operation.
2. Description of the Prior Art
FIG. 1
is a block diagram showing a memory core circuit in a conventional static random access memory (SRAM). In
FIG. 1
, each memory cell MC in a memory cell array
100
in the memory core circuit is placed at each cross point of a plurality of bit line pairs BL and bBL (BL
0
and bBL
0
, BL
1
and bBL
1
,) and a plurality of word lines WL (WL
0
, WL
1
, . . . ).
PMOS transistors QP
1
and QP
2
as bit line loads are connected to one end of each bit line pair BL and bBL. Other end of each bit line pair BL and bBL is connected to data line pair DL and bDL through each column gate
105
which is made up of NMOS transistors QN
1
and QN
2
.
The data line pair DL and bDL is connected to a write-in driver
103
for data write-in operation, and also connected to a sense amplifier (SA)
102
for data readout operation.
FIG. 2
is a timing chart showing a data write operation and a write recovery operation in the conventional SRAM shown in FIG.
1
.
When a data item is written into one memory cell MC, as shown in
FIG. 2
, the level of a write enable signal /WE is switched to a L level. One of the data line pair DL and bDL becomes the L level and other becomes a H level according to the value of the write-in data. These levels of the data line pairs DL and bDL are transferred to the bit line pair which are selected by the column gate
105
. Further, the levels of the data line pair DL and bDL are written into the memory cell MC that is selected by a word line WL (WL
0
, WL
1
, . . . WLn). After the completion of the data write-in operation to the memory cell MC, the write enable signal /WE is switched to the H level, and a write recovery operation is performed. In the write recovery operation, the levels of both the bit lines BL and bBL in each bit line pair are set to the H level for the following data readout operation or the following data write-in operation. In the write recovery operation, the level of the precharge signal /PCH becomes the L level and the PMOS transistors QP and QP
2
as the bit line loads enter an ON state (an active state).
Because both the capacity of the bit lines and the capacity of the data lines become large in large scale semiconductor integrated circuits, it is difficult to execute the write recovery operation at a high speed rate only by using the write-in driver
103
. In order to avoid this conventional drawback, both the PMOS transistors QP
1
and QP
2
as the bit line loads in the conventional SRAM shown in
FIG. 2
enter the ON state during the write recovery operation by setting the L level to the precharge signal /PCH. Thereby, the bit line pair BL and bBL can be charged rapidly.
During both the data write-in operation and the data readout operation, the level of this precharge signal is kept at the H level (namely, /PCH=H).
However, such a conventional control method of the bit line recovery operation which is performed in the DRAM having the configuration shown in
FIG. 1
, it must be necessary to adjust both the timing of the ON/OFF operation of the write-in driver
103
and the timing of the ON/OFF of the PMOS transistors QP
1
and QP
2
as the bit line loads for the bit lines BL and bBL. When both the timings are not matched to each other, it happens that a write-in data item changes to a wrong data item, or a waste power consumption increases. Furthermore, because the recovery operation for the bit lines by the PMOS transistors QP
1
and QP
2
is performed for all of the bit lines BL and bBL (BL
0
, bBL
0
, BL
1
, bBL
1
, . . . ) which are selected by the word lines, the large power consumption for the gate capacitances of the PMOS transistors QP
1
and QP
2
(as the bit line loads) increases.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional semiconductor memory device, to provide a semiconductor memory device of a low power consumption with an improved timing margin which is capable of performing the recovery operation for the bit lines automatically only by the control of the write-in driver without any elapse of the timings between the ON/OFF operation of the PMOS transistors as the bit line loads and the ON/OFF operation of the write-in driver.
In accordance with a preferred embodiment of the present invention, a semiconductor memory device has a memory cell array, a write-in driver, a sense amplifier, and bit line loads. The memory cell array includes memory cells which are located at cross points of word lines and bit lines. The write-in driver performs data write-in operation to transfer write-in data to the memory cells through the bit lines, and performs a recovery operation by supplying a high level voltage to the bit lines when a voltage potential of the bit lines drops to a low voltage potential after a completion of the data write-in operation. The sense amplifier detects and amplifies data read from the memory cells through the bit lines. The operation of the bit line loads is controlled by the voltage potential of the bit lines. Each bit line load is placed between a first power source and each of the bit lines. The bit line load enters the ON state in order to accelerate the recovery operation when the voltage potential of the bit lines reach to a predetermined voltage potential during the recovery operation performed by the write-in driver. Thereby, the bit line loads for the bit lines are controlled automatically by the voltage potential of the bit lines and enters the ON state when the voltage potential of the bit lines is over a predetermined voltage level in order to accelerate the speed of the recovery operation. Accordingly, it is not necessary to match the timings between the write-in driver and the bit line loads. This feature of the present invention causes to increase a timing margin and to suppress the power consumption to be used for the control of the bit line loads.
In addition, in a semiconductor memory device as another preferred embodiment of the present invention, each of the bit line loads includes a PMOS transistor whose drain is connected to the corresponding bit line and whose source is connected to the first power source, and an inverter connected between the corresponding bit line and a gate of the PMOS transistor for inverting a voltage potential of the corresponding bit line and transferring the inverted voltage potential to the gate of the PMOS transistor. Thereby, during the recovery operation performed by the write-in driver, the PMOS transistor enters the ON state automatically when the voltage of the bit line, whose voltage potential has dropped to a low voltage potential, reaches to and over a threshold voltage of the PMOS transistor. The entering to the ON state of the PMOS transistor causes to increase the voltage potential of the bit lines rapidly to the H level. On the other hand, during a data write-in operation, because the PMOS transistor enters the OFF state when the voltage potential of the bit line to be shifted to the L level drops under a threshold voltage of the inverter, no waste current flows through the bit line and it is thereby possible to perform the data write-in operation at high speed.
Furthermore, in a semiconductor memory device as another preferred embodiment of the present invention, each of the bit line loads further includes a NMOS transistor connected to the PMOS transistor in series. In the semiconductor memory device, a drain of the NMOS transistor is connected to both the corresponding bit line and the drain of the PMOS transistor, and a source of the NMOS transistor is connected to a second power source, and a gate of the NMOS transistor is connected to the inverter in order to supply an output of the inverter. Thereby, each bit line load i

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