Semiconductor memory device capable of adjusting impedance...

Details Semiconductor memory device capable of adjusting impedance... Semiconductor memory device capable of adjusting impedance...

2006-03-28

2006-03-28

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S026000, C365S189050

Reexamination Certificate

active

07019556

ABSTRACT:
A semiconductor memory device comprises a data input/output pad; a data input unit for buffering and latching a data signal inputted through the data input/output pad during a data access operation, or for buffering and latching an OCD control code signal inputted through the data input/output pad during the OCD calibration control operation; a data align unit for aligning the data signal latched by the data input unit and transferring the aligned data signal to a memory core during the data access operation, or for aligning and outputting the OCD control code signal latched by the data input unit during the OCD calibration control operation; a data output driver for outputting and driving the data signal outputted from the memory core; and an OCD control unit for decoding the OCD control code signal outputted from the data align unit to thereby adjust an output impedance of the data output driver.

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